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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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H8/3657 Series HD6473657, HD6433657 H8/3656 HD6433656 H8/3655 HD6433655 H8/3654 HD6433654 H8/3653 HD6433653 H8/3652 HD6433652 Hardware Manual Preface The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core, with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. The H8/3657 Series has a system-on-a-chip architecture that includes such peripheral functions as a five timers, a 14-bit PWM, a two-channel serial communication interface, and an A/D converter. This makes it ideal for use in advanced control systems. This manual describes the hardware of the H8/3657 Series. For details on the H8/3657 Series instruction set, refer to the H8/300L Series Programming Manual. Contents Section 1 1.1 1.2 1.3 Overview.......................................................................................................... Overview......................................................................................................................... Internal Block Diagram .................................................................................................. Pin Arrangement and Functions ..................................................................................... 1.3.1 Pin Arrangement................................................................................................. 1.3.2 Pin Functions ...................................................................................................... 1 1 5 6 6 8 Section 2 2.1 CPU................................................................................................................... 11 11 11 12 12 13 13 13 15 15 16 17 18 18 20 24 26 28 29 29 31 35 37 38 40 40 41 43 43 44 44 44 45 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Overview......................................................................................................................... 2.1.1 Features............................................................................................................... 2.1.2 Address Space..................................................................................................... 2.1.3 Register Configuration........................................................................................ Register Descriptions...................................................................................................... 2.2.1 General Registers................................................................................................ 2.2.2 Control Registers ................................................................................................ 2.2.3 Initial Register Values ........................................................................................ Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ..................................................................... 2.3.2 Memory Data Formats........................................................................................ Addressing Modes .......................................................................................................... 2.4.1 Addressing Modes .............................................................................................. 2.4.2 Effective Address Calculation ............................................................................ Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .................................................................................. 2.5.2 Arithmetic Operations ........................................................................................ 2.5.3 Logic Operations ................................................................................................ 2.5.4 Shift Operations .................................................................................................. 2.5.5 Bit Manipulations ............................................................................................... 2.5.6 Branching Instructions........................................................................................ 2.5.7 System Control Instructions ............................................................................... 2.5.8 Block Data Transfer Instruction ......................................................................... Basic Operational Timing............................................................................................... 2.6.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 2.6.2 Access to On-Chip Peripheral Modules ............................................................. CPU States ...................................................................................................................... 2.7.1 Overview............................................................................................................. 2.7.2 Program Execution State ................................................................................... 2.7.3 Program Halt State.............................................................................................. 2.7.4 Exception-Handling State................................................................................... Memory Map .................................................................................................................. 2.9 Application Notes ........................................................................................................... 2.9.1 Notes on Data Access ......................................................................................... 2.9.2 Notes on Bit Manipulation.................................................................................. 2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 46 46 48 54 Section 3 3.1 3.2 Exception Handling...................................................................................... 55 55 55 55 55 57 57 57 59 68 69 70 75 76 76 77 3.3 3.4 Overview......................................................................................................................... Reset ............................................................................................................................ 3.2.1 Overview............................................................................................................. 3.2.2 Reset Sequence ................................................................................................... 3.2.3 Interrupt Immediately after Reset....................................................................... Interrupts......................................................................................................................... 3.3.1 Overview............................................................................................................. 3.3.2 Interrupt Control Registers ................................................................................. 3.3.3 External Interrupts .............................................................................................. 3.3.4 Internal Interrupts ............................................................................................... 3.3.5 Interrupt Operations............................................................................................ 3.3.6 Interrupt Response Time..................................................................................... Application Notes ........................................................................................................... 3.4.1 Notes on Stack Area Use .................................................................................... 3.4.2 Notes on Rewriting Port Mode Registers ........................................................... Section 4 4.1 Clock Pulse Generators............................................................................... 79 79 79 79 80 83 85 86 4.2 4.3 4.4 4.5 Overview......................................................................................................................... 4.1.1 Block Diagram.................................................................................................... 4.1.2 System Clock and Subclock ............................................................................... System Clock Generator ................................................................................................. Subclock Generator ........................................................................................................ Prescalers ........................................................................................................................ Note on Oscillators ......................................................................................................... Section 5 5.1 5.2 Power-Down Modes..................................................................................... 87 87 90 95 95 95 95 96 96 96 97 98 5.3 5.4 Overview......................................................................................................................... 5.1.1 System Control Registers ................................................................................... Sleep Mode ..................................................................................................................... 5.2.1 Transition to Sleep Mode.................................................................................... 5.2.2 Clearing Sleep Mode .......................................................................................... 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode ............................................ Standby Mode................................................................................................................. 5.3.1 Transition to Standby Mode ............................................................................... 5.3.2 Clearing Standby Mode ...................................................................................... 5.3.3 Oscillator Settling Time after Standby Mode is Cleared.................................... Watch Mode.................................................................................................................... 5.5 5.6 5.7 5.8 5.4.1 Transition to Watch Mode .................................................................................. 98 5.4.2 Clearing Watch Mode......................................................................................... 98 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ...................................... 98 Subsleep Mode................................................................................................................ 99 5.5.1 Transition to Subsleep Mode .............................................................................. 99 5.5.2 Clearing Subsleep Mode..................................................................................... 99 Subactive Mode .............................................................................................................. 100 5.6.1 Transition to Subactive Mode............................................................................. 100 5.6.2 Clearing Subactive Mode ................................................................................... 100 5.6.3 Operating Frequency in Subactive Mode ........................................................... 100 Active (Medium-Speed) Mode ....................................................................................... 101 5.7.1 Transition to Active (Medium-Speed) Mode ..................................................... 101 5.7.2 Clearing Active (Medium-Speed) Mode ............................................................ 101 5.7.3 Operating Frequency in Active (Medium-Speed) Mode .................................... 101 Direct Transfer................................................................................................................ 102 Section 6 6.1 6.2 6.3 6.4 ROM.................................................................................................................. 105 Overview......................................................................................................................... 105 6.1.1 Block Diagram.................................................................................................... 105 PROM Mode................................................................................................................... 106 6.2.1 Setting to PROM Mode ..................................................................................... 106 6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 106 Programming .................................................................................................................. 109 6.3.1 Writing and Verifying......................................................................................... 109 6.3.2 Programming Precautions................................................................................... 114 Reliability of Programmed Data..................................................................................... 115 Section 7 7.1 RAM ................................................................................................................. 117 Overview......................................................................................................................... 117 7.1.1 Block Diagram.................................................................................................... 117 I/O Ports........................................................................................................... 119 Overview......................................................................................................................... 119 Port 1 ............................................................................................................................ 121 8.2.1 Overview............................................................................................................. 121 8.2.2 Register Configuration and Description ............................................................. 121 8.2.3 Pin Functions ...................................................................................................... 125 8.2.4 Pin States ............................................................................................................ 126 8.2.5 MOS Input Pull-Up............................................................................................. 126 Port 2 ............................................................................................................................ 127 8.3.1 Overview............................................................................................................. 127 8.3.2 Register Configuration and Description ............................................................. 127 8.3.3 Pin Functions ...................................................................................................... 129 Section 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.3.4 Pin States ............................................................................................................ 130 Port 3 ............................................................................................................................ 131 8.4.1 Overview............................................................................................................. 131 8.4.2 Register Configuration and Description ............................................................. 131 8.4.3 Pin Functions ...................................................................................................... 135 8.4.4 Pin States ............................................................................................................ 136 8.4.5 MOS Input Pull-Up............................................................................................. 136 Port 5 ............................................................................................................................ 137 8.5.1 Overview............................................................................................................. 137 8.5.2 Register Configuration and Description ............................................................. 137 8.5.3 Pin Functions ...................................................................................................... 139 8.5.4 Pin States ............................................................................................................ 140 8.5.5 MOS Input Pull-Up............................................................................................. 140 Port 6 ............................................................................................................................ 141 8.6.1 Overview............................................................................................................. 141 8.6.2 Register Configuration and Description ............................................................. 141 8.6.3 Pin Functions ...................................................................................................... 143 8.6.4 Pin States ............................................................................................................ 143 Port 7 ............................................................................................................................ 144 8.7.1 Overview............................................................................................................. 144 8.7.2 Register Configuration and Description ............................................................. 144 8.7.3 Pin Functions ...................................................................................................... 146 8.7.4 Pin States ............................................................................................................ 146 Port 8 ............................................................................................................................ 147 8.8.1 Overview............................................................................................................. 147 8.8.2 Register Configuration and Description ............................................................. 147 8.8.3 Pin Functions ...................................................................................................... 149 8.8.4 Pin States ............................................................................................................ 150 Port 9 ............................................................................................................................ 151 8.9.1 Overview............................................................................................................. 151 8.9.2 Register Configuration and Description ............................................................. 151 8.9.3 Pin Functions ...................................................................................................... 152 8.9.4 Pin States ............................................................................................................ 152 Port B ............................................................................................................................ 153 8.10.1 Overview............................................................................................................. 153 8.10.2 Register Configuration and Description ............................................................. 153 8.10.3 Pin Functions ...................................................................................................... 154 8.10.4 Pin States ............................................................................................................ 154 Usage Notes .................................................................................................................... 154 Section 9 9.1 9.2 Timers............................................................................................................... 155 Overview......................................................................................................................... 155 Timer A........................................................................................................................... 156 9.2.1 Overview............................................................................................................. 156 9.3 9.4 9.5 9.6 9.2.2 Register Descriptions.......................................................................................... 158 9.2.3 Timer Operation.................................................................................................. 160 9.2.4 Timer A Operation States ................................................................................... 161 Timer B1......................................................................................................................... 162 9.3.1 Overview............................................................................................................. 162 9.3.2 Register Descriptions.......................................................................................... 163 9.3.3 Timer Operation.................................................................................................. 165 9.3.4 Timer B1 Operation States ................................................................................. 166 Timer V........................................................................................................................... 167 9.4.1 Overview............................................................................................................. 167 9.4.2 Register Descriptions.......................................................................................... 170 9.4.3 Timer Operation.................................................................................................. 176 9.4.4 Timer V Operation Modes.................................................................................. 181 9.4.5 Interrupt Sources................................................................................................. 181 9.4.6 Application Examples......................................................................................... 182 9.4.7 Application Notes ............................................................................................... 184 Timer X........................................................................................................................... 190 9.5.1 Overview............................................................................................................. 190 9.5.2 Register Descriptions.......................................................................................... 194 9.5.3 CPU Interface ..................................................................................................... 205 9.5.4 Timer Operation.................................................................................................. 208 9.5.5 Timer X Operation Modes.................................................................................. 217 9.5.6 Interrupt Sources................................................................................................. 217 9.5.7 Timer X Application Example............................................................................ 218 9.5.8 Application Notes ............................................................................................... 219 Watchdog Timer ............................................................................................................. 224 9.6.1 Overview............................................................................................................. 224 9.6.2 Register Descriptions.......................................................................................... 225 9.6.3 Timer Operation.................................................................................................. 228 9.6.4 Watchdog Timer Operation States...................................................................... 229 Section 10 Serial Communication Interface............................................................... 231 10.1 10.2 Overview......................................................................................................................... 231 SCI1 ............................................................................................................................ 231 10.2.1 Overview............................................................................................................. 231 10.2.2 Register Descriptions.......................................................................................... 233 10.2.3 Operation in Synchronous Mode ........................................................................ 239 10.2.4 Operation in SSB Mode...................................................................................... 242 10.2.5 Interrupts............................................................................................................. 244 SCI3 ............................................................................................................................ 245 10.3.1 Overview............................................................................................................. 245 10.3.2 Register Descriptions.......................................................................................... 248 10.3.3 Operation ............................................................................................................ 267 10.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 Operation in Asynchronous Mode...................................................................... 271 Operation in Synchronous Mode ........................................................................ 280 Multiprocessor Communication Function .......................................................... 287 Interrupts............................................................................................................. 294 Application Notes ............................................................................................... 295 Section 11 14-Bit PWM ................................................................................................... 299 11.1 Overview......................................................................................................................... 299 11.1.1 Features............................................................................................................... 299 11.1.2 Block Diagram.................................................................................................... 299 11.1.3 Pin Configuration................................................................................................ 300 11.1.4 Register Configuration........................................................................................ 300 Register Descriptions...................................................................................................... 301 11.2.1 PWM Control Register (PWCR) ........................................................................ 301 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 302 Operation ........................................................................................................................ 303 11.2 11.3 Section 12 A/D Converter................................................................................................ 305 12.1 Overview......................................................................................................................... 305 12.1.1 Features............................................................................................................... 305 12.1.2 Block Diagram.................................................................................................... 305 12.1.3 Pin Configuration................................................................................................ 306 12.1.4 Register Configuration........................................................................................ 306 Register Descriptions...................................................................................................... 307 12.2.1 A/D Result Register (ADRR) ............................................................................. 307 12.2.2 A/D Mode Register (AMR) ................................................................................ 307 12.2.3 A/D Start Register (ADSR) ................................................................................ 309 Operation ........................................................................................................................ 310 12.3.1 A/D Conversion Operation ................................................................................. 310 12.3.2 Start of A/D Conversion by External Trigger Input ........................................... 310 Interrupts......................................................................................................................... 311 Typical Use..................................................................................................................... 311 Application Notes ........................................................................................................... 314 12.2 12.3 12.4 12.5 12.6 Section 13 Electrical Characteristics ............................................................................ 315 13.1 13.2 Absolute Maximum Ratings ........................................................................................... 315 Electrical Characteristics ................................................................................................ 316 13.2.1 Power Supply Voltage and Operating Range ..................................................... 316 13.2.2 DC Characteristics (HD6473657)....................................................................... 318 13.2.3 AC Characteristics (HD6473657)....................................................................... 324 13.2.4 DC Characteristics (HD6433657, HD6433656, HD6433655, HD6433654, HD6433653, HD6433652)............................................................ 327 13.3 13.4 13.2.5 AC Characteristics (HD6433657, HD6433656, HD6433655, HD6433654, HD6433653, HD6433652)............................................................ 333 13.2.6 A/D Converter Characteristics............................................................................ 336 Operation Timing............................................................................................................ 337 Output Load Circuit........................................................................................................ 340 Appendix A CPU Instruction Set .................................................................................. 341 A.1 A.2 A.3 Instructions ..................................................................................................................... 341 Operation Code Map....................................................................................................... 349 Number of Execution States ........................................................................................... 351 Appendix B Internal I/O Register ................................................................................. 358 B.1 B.2 Addresses........................................................................................................................ 358 Functions......................................................................................................................... 362 Appendix C I/O Port Block Diagrams......................................................................... 407 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Block Diagrams of Port 1 ............................................................................................... Block Diagrams of Port 2 ............................................................................................... Block Diagrams of Port 3 ............................................................................................... Block Diagrams of Port 5 ............................................................................................... Block Diagram of Port 6................................................................................................. Block Diagrams of Port 7 ............................................................................................... Block Diagrams of Port 8 ............................................................................................... Block Diagram of Port 9................................................................................................. Block Diagram of Port B ................................................................................................ 407 413 417 421 424 425 429 437 438 Appendix D Port States in the Different Processing States................................... 439 Appendix E Product Code Lineup................................................................................ 440 Appendix F Package Dimensions................................................................................. 441 Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3657 Series of microcomputers are equipped with a UART (Universal Asynchronous Receiver/Transmitter). Other on-chip peripheral functions include five timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, and an A/D converter. Together, these functions make the H8/3657 Series ideally suited for embedded applications in advanced control systems. The ZTATTM* versions of the H8/3657 come with userprogrammable PROM. Table 1 summarizes the features of the H8/3657 Series.. Table 1 summarizes the features of the H8/3657 Series. Note: * ZTAT is a trademark of Hitachi, Ltd. Table 1-1 Features Item CPU Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) * Operating speed -- Max. operating speed: 5 MHz -- Add/subtract: 0.4 s (operating at 5 MHz) -- Multiply/divide: 2.8 s (operating at 5 MHz) -- Can run on 32.768 kHz subclock * Instruction set compatible with H8/300 CPU -- Instruction length of 2 bytes or 4 bytes -- Basic arithmetic operations between registers -- MOV instruction for data transfer between memory and registers * Typical instructions -- Multiply (8 bits x 8 bits) -- Divide (16 bits / 8 bits) -- Bit accumulator -- Register-indirect designation of bit position 1 Table 1-1 Features (cont) Item Interrupts Description 33 interrupt sources * 12 external interrupt sources (IRQ3 to IRQ0, INT7 to INT0) * 21 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators * System clock pulse generator: 1 to 10 MHz * Subclock pulse generator: 32.768 kHz Power-down modes Seven power-down modes * Sleep (high-speed) mode * Sleep (medium-speed) mode * Standby mode * Watch mode * Subsleep mode * Subactive mode * Active (medium-speed) mode Memory Large on-chip memory * H8/3657: 60-kbyte ROM, 2-kbyte RAM * H8/3656: 48-kbyte ROM, 2-kbyte RAM * H8/3655: 40-kbyte ROM, 2-kbyte RAM * H8/3654: 32-kbyte ROM, 1 kbyte RAM * H8/3653: 24-kbyte ROM, 1 kbyte RAM * H8/3652: 16-kbyte ROM, 1 kbyte RAM I/O ports 67 pins * 59 I/O pins * 8 input pins Timers Five on-chip timers * Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (o)* and four clock signals divided from the watch clock (ow)* * Timer B1: 8-bit timer -- Count-up timer with selection of seven internal clock signals or event input from external pin -- Auto-reloading Note: * o and oW are defined in section 4, Clock Pulse Generators. 2 Table 1-1 Features (cont) Item Timers Description * Timer V: 8-bit timer -- Count-up timer with selection of six internal clock signals or event input from external pin -- Compare-match waveform output -- Incrementing specifiable by external trigger input * Timer X: 16-bit timer -- Count-up timer with selection of three internal clock signals or event input from external pin -- Output compare (2 output pins) -- Input capture (4 input pins) * Watchdog timer -- Reset signal generated by 8-bit counter overflow Serial communication interface Two channels on chip * SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer * SCI3: 8-bit synchronous/asynchronous serial interface Incorporates multiprocessor communication function 14-bit PWM Pulse-division PWM output for reduced ripple * Can be used as a 14-bit D/A converter by connecting to an external low-pass filter. A/D converter Successive approximations using a resistance ladder * 8-channel analog input pins * Conversion time: 31/o or 62/o per channel 3 Table 1-1 Features (cont) Item Product lineup Mask ROM Version HD6433657W HD6433657X HD6433657H HD6433657F HD6433656W HD6433656X HD6433656H HD6433656F HD6433655W HD6433655X HD6433655H HD6433655F HD6433654W HD6433654X HD6433654H HD6433654F HD6433653W HD6433653X HD6433653H HD6433653F HD6433652W HD6433652X HD6433652H HD6433652F Specification Product Code ZTATTM Version HD6473657W HD6473657X HD6473657H HD6473657F -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Package 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) ROM 16 kbytes RAM 1 kbyte ROM 24 kbytes RAM 1 kbyte ROM 32 kbytes RAM 1 kbyte ROM 40 kbytes RAM 2 kbytes ROM 48 kbytes RAM 2 kbytes ROM/RAM Size ROM 60 kbytes RAM 2 kbytes 4 1.2 Internal Block Diagram Figure 1-1 shows a block diagram of the H8/3657 Series. OSC1 OSC2 System clock generator Subclock generator X1 X2 VSS VCC RES IRQ0 TEST CPU H8/300L Data bus (upper) Address bus Data bus (lower) P10/TMOW P11 P12 P13 P14/PWM P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD P23 P24 P25 P26 P27 P30/SCK1 P31/SI1 P32/SO1 P33 P34 P35 Port 1 ROM RAM P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI Port 8 Port 7 Port 6 Port 5 Timer A Port 2 SCI1 Timer B1 SCI3 P77 P76/TMOV P75/TMCIV P74/TMRIV P73 P72 P71 P70 Port 3 Timer X Timer V P67 P66 P65 P64 P63 P62 P61 P60 P90 P91 P92 P93 P94 Port 9 Watchdog timer 14-bit PWM A/D converter P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0 Port B AVCC AVSS PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 Figure 1-1 Block Diagram 5 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/3657 Series pin arrangement is shown in figures 1-2 (TFP-80C, TFP-80F, FP-80A), and in figures 1-3 (FP-80B). P17/IRQ3/TRGV P16/IRQ2 P10/TMOW P14/PWM P15/IRQ1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVSS TEST X2 X1 VSS OSC1 OSC2 RES VCC P90 P91 P92 P93 P94 IRQ0 P50/INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 P21/RXD 60 59 58 57 56 55 54 53 P13 P27 P22/TXD PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 AVCC P12 P11 P26 P25 P24 P23 P20/SCK3 P35 P34 P33 P32/SO1 P31/SI1 P30/SCK1 VCC VSS P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI P77 P76/TMOV P75/TMCIV H8/3657 Series TFP-80C, TFP-80F, FP-80A 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 P73 P55/INT5/ADTRG P56/INT6/TMIB Figure 1-2 Pin Arrangement (TFP-80C, TFP-80F, FP-80A: Top View) 6 P74/TMRIV P51/INT1 P52/INT2 P53/INT3 P54/INT4 P57/INT7 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 40 P17/IRQ3/TRGV P10/TMOW P14/PWM P16/IRQ2 P15/IRQ1 PB6/AN6 PB7/AN7 AVCC P13 P12 P11 P27 P26 P25 P24 66 80 79 78 77 76 75 74 73 72 71 70 69 68 67 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 AVSS TEST X2 X1 VSS OSC1 OSC2 RES VCC P90 P91 P92 P93 P94 IRQ0 P50/INT0 P51/INT1 P52/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 FP-80B 65 64 63 62 61 60 59 58 57 P23 P22/TXD P21/RXD P20/SCK3 P35 P34 P33 P32/SO1 P31/SI1 P30/SCK1 VCC VSS P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI P77 P76/TMOV P75/TMCIV P74/TMRIV P73 H8/3657 Series 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P55/INT5/ADTRG P56/INT6/TMIB P57/INT7/ P53/INT3 P54/INT4 P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 Figure 1-3 Pin Arrangement (FP-80B: Top View) 7 P72 1.3.2 Pin Functions Table 1-2 outlines the pin functions of the H8/3657 Series. Table 1-2 Pin Functions Pin No. TFP-80C, TFP-80F, FP-80A FP-80B 13, 53 15, 55 Type Symbol I/O Input Name and Functions Power supply: All VCC pins should be connectedto the system power supply (+5 V) Ground: All VSS pins should be connected to the system power supply (0 V) Analog power supply: This is the power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Analog ground: This is the A/D converter ground pin. It should be connected to the system power supply (0 V). System clock: These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram. Subclock: These pins connect to a 32.768-kHz crystal oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. Reset: When this pin is driven low, the chip is reset Test: This is a test pin, not for use in application systems. It should be connected to VSS. IRQ interrupt request 0 to 3: These are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge INT interrupt request 0 to 7: These are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge Clock output: This is an output pin for waveforms generated by the timer A output circuit Power VCC source pins VSS AVCC 9, 52 76 11, 54 78 Input Input AVSS 5 7 Input Clock pins OSC1 OSC2 10 11 12 13 Input Output X1 X2 System control RES TEST 8 7 12 6 10 9 14 8 Input Output Input Input Interrupt pins IRQ0 IRQ1 IRQ2 IRQ3 INT7 to INT0 19 73 74 75 27 to 20 21 75 76 77 29 to 22 Input Input Timer pins TMOW 68 70 Output 8 Table 1-2 Pin Functions (cont) Pin No. TFP-80C, TFP-80F, FP-80A FP-80B 26 28 Type Timer pins Symbol TMIB I/O Input Name and Functions Timer B1 event counter input: This is an event input pin for input to the timer B1 counter Timer V output: This is an output pin for waveforms generated by the timer V output compare function Timer V event input: This is an event input pin for input to the timer V counter Timer V counter reset: This is a counter reset input pin for timer V Timer V counter trigger input: This is a trigger input pin for the timer V counter and realtime output port Timer X clock input: This is an external clock input pin for input to the timer X counter Timer X output compare A output: This is an output pin for timer X output compare A Timer X output compare B output: This is an output pin for timer X output compare B Timer X input capture A input: This is an input pin for timer X input capture A Timer X input capture B input: This is an input pin for timer X input capture B Timer X input capture C input: This isan input pin for timer X input capture C Timer X input capture D input: This is an input pin for timer X input capture D 14-bit PWM output: This is an output pin for waveforms generated by the 14-bit PWM Port B: This is an 8-bit input port Port 1: This is a 8-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1) TMOV 42 44 Output TMCIV TMRIV TRGV 41 40 75 43 42 77 Input Input Input FTCI 44 46 Input FTOA 45 47 Output FTOB 46 48 Output FTIA FTIB FTIC FTID 14-bit PWM pin I/O ports PWM 47 48 49 50 72 49 50 51 52 74 Input Input Input Input Output PB7 to PB0 P17 to P10 77 to 80, 1 to 4 75 to 68 79 to 80 1 to 6 77 to 70 Input I/O 9 Table 1-2 Pin Functions (cont) Pin No. TFP-80C, TFP-80F, FP-80A FP-80B 67 to 60 59 to 54 27 to 20 35 to 28 43 to 36 51 to 44 18 to 14 55 56 54 61 62 60 77 to 80, 1 to 4 25 69 to 62 61 to 56 29 to 22 37 to 30 45 to 38 53 to 46 20 to 16 57 58 56 63 64 62 79, 80 1 to 6 27 Type I/O ports Symbol P27 to P20 P35 to P30 P57 to P50 P67 to P60 P77 to P70 P87 to P80 P94 to P90 I/O I/O Name and Functions Port 2: This is a 8-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2) Port 3: This is a 6-bit I/O port. Input or output can be designated for each bit by means of port control register 3 (PCR3) Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5) Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6) Port 7: This is a 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7) Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8) Port 9: This is a 5-bit I/O port. Input or output can be designated for each bit by means of port control register 9 (PCR9) SCI1 receive data input: This is the SCI1 data input pin SCI1 transmit data output: This is the SCI1 data output pin SCI1 clock I/O : This is the SCI1 clock I/O pin SCI3 receive data input: This is the SCI3 data input pin SCI3 transmit data output: TThis is the SCI3 data output pin SCI3 clock I/O: This is the SCI3 clock I/O pin Analog input channels 7 to 0: These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter I/O I/O I/O I/O I/O I/O Serial communication interface (SCI) SI1 SO1 SCK1 RXD TXD SCK3 Input Output I/O Input Output I/O Input A/D converter AN7 to An0 ADTRG Input 10 Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers Instruction set with 55 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions Eight addressing modes -- Register direct -- Register indirect -- Register indirect with displacement -- Register indirect with post-increment or pre-decrement -- Absolute address -- Immediate -- Program-counter relative -- Memory indirect 64-kbyte address space High-speed operation -- All frequently used instructions are executed in two to four states -- High-speed arithmetic and logic operations -- 8- or 16-bit register-register add or subtract: 0.4 s* -- 8 x 8-bit multiply: 2.8 s* -- 16 / 8-bit divide: 2.8 s* Low-power operation modes SLEEP instruction for transfer to low-power operation * * * * * Note: * These values are at o = 5 MHz. 11 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0 Control registers (CR) 15 PC 76543210 CCR I U H U N Z V C 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2-1 CPU Registers 12 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0 when the instruction code is read). 13 Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see section 3.3, Interrupts. Bit 6--User Bit (U): Can be used freely by the user. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be used freely by the user. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Stores the value of the most significant bit. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 14 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. * * * 15 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 don't care 7 0 1-bit data RnL don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB don't care 7 0 LSB Byte data RnL don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL don't care Notation: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 16 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB CCR: Condition code register Note: * Ignored on return Figure 2-4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 17 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. 1 2 3 4 5 6 7 8 Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 3. 18 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The displacement should be an even number. 19 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2-2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. 20 Table 2-2 Effective Address Calculation Effective Address Calculation Method 3 0 3 No. rm 43 0 Addressing Mode and Instruction Format Effective Address (EA) 0 1 Register direct, Rn rn 15 87 op 15 0 rm Contents (16 bits) of register indicated by rm 15 43 0 rn Operand is contents of registers indicated by rm/rn 0 2 Register indirect, @Rn 15 76 op 15 0 rm 3 Contents (16 bits) of register indicated by rm 43 0 Register indirect with displacement, @(d:16, Rn) rm disp 15 0 15 76 21 15 op disp 0 15 0 4 43 0 Register indirect with post-increment, @Rn+ rm Contents (16 bits) of register indicated by rm 15 76 op 15 1 or 2 0 Register indirect with pre-decrement, @-Rn 43 0 Contents (16 bits) of register indicated by rm 15 0 15 76 op rm Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size Table 2-2 Effective Address Calculation (cont) Effective Address Calculation Method 15 87 No. H'FF 0 Addressing Mode and Instruction Format Effective Address (EA) 5 Absolute address @aa:8 abs 15 0 0 15 87 op @aa:16 0 15 op abs 6 0 Immediate #xx:8 IMM Operand is 1- or 2-byte immediate data 0 22 15 15 87 op #xx:16 15 op IMM 0 7 Program-counter relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp Table 2-2 Effective Address Calculation (cont) Effective Address Calculation Method Effective Address (EA) No. Addressing Mode and Instruction Format 8 0 Memory indirect, @@aa:8 15 87 op 15 87 0 abs H'00 15 abs 0 Memory contents (16 bits) 23 Notation: rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3. Table 2-3 Instruction Set Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instructions MOV, PUSH*1, POP*1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Number 1 14 4 8 14 5 8 1 Total: 55 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine language. 2. Bcc is a conditional branch instruction in which cc represents a condition code. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. 24 Notation Rd Rs Rn (EAd), 25 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction MOV Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. Notes: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details. 26 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn @-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op Notation: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @-SP Figure 2-5 Data Transfer Instruction Codes 27 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. Table 2-5 Arithmetic Instructions Instruction ADD SUB Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or addition or subtraction with carry on immediate data and data in a general register. Rd 1 Rd Increments or decrements a general register Rd 1 Rd, Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and indicates the result in the CCR. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register ADDX SUBX B INC DEC ADDS SUBS DAA DAS MULXU B W B B DIVXU B CMP B/W NEG B Notes: * Size: Operand size B: Byte W: Word 28 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. Table 2-6 Logic Operation Instructions Instruction AND Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Notes: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Table 2-7 Shift Instructions Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents B Rd shift Rd Performs a logical shift operation on general register contents B Rd rotate Rd Rotates general register contents B Rd rotate through carry Rd Rotates general register contents through the C (carry) bit Notes: * Size: Operand size B: Byte 29 Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#XX:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Notation: op: Operation field rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 30 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction BSET Size* B Function 1 ( 31 Table 2-8 Bit-Manipulation Instructions (cont) Instruction BXOR Size* B Function C ( Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 32 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 33 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Notation: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes (cont) 34 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Bcc Size -- Function Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine 35 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Notation: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2-8 Branching Instruction Codes 36 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Instruction RTE SLEEP LDC Size* -- -- B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details. Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR #IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR #IMM CCR Logically ORs the condition code register with immediate data XORC B CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data NOP -- PC + 2 PC Only increments the program counter Notes: * Size: Operand size B: Byte 37 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op IMM ANDC, ORC, XORC, LDC (#xx:8) Notation: op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction Instruction EEPMOV Size -- Function If R4L 0 then repeat until else next; Block transfer instruction. Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6. After the transfer, the next instruction is executed. @R5+ @R6+ R4L - 1 R4L R4L = 0 Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details. 38 15 8 7 0 op op Notation: op: Operation field Figure 2-10 Block Data Transfer Instruction Code 39 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (o) or a subclock (oSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of o or oSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2-11 shows the on-chip memory access cycle. Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-11 On-Chip Memory Access Cycle 40 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle. Two-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access) 41 Three-state access to on-chip peripheral modules Bus cycle T1 state o or o SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access) 42 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2-14. Figure 2-15 shows the state transitions. CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep (high-speed) mode Sleep (medium-speed) mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2-14 CPU Operation States 43 Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source occurs Interrupt source occurs Exceptionhandling complete Program halt state SLEEP instruction executed Program execution state Figure 2-15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are four modes: two sleep modes (high speed and medium speed), standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see section 3.3, Interrupts. 44 2.8 Memory Map Figure 2-16 shows a memory map of the H8/3657 Series. H8/3652 H'0000 Interrupt vectors H'002F H'0030 16 kbytes H8/3653 H8/3654 H8/3655 H8/3656 H8/3657 24 kbytes H'3FFF 32 kbytes On-chip ROM H'5FFF 40 kbytes 48 kbytes 60 kbytes H'7FFF H'9FFF H'BFFF H'EDFF H'EE00 H'F770 Internal I/O registers (16 bytes) H'F77F H'F780 2 kbytes H'FB80 On-chip RAM H'FF7F H'FF80 Reserved H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF 1 kbytes Reserved Figure 2-16 H8/3657 Series Memory Map 45 2.9 Application Notes 2.9.1 Notes on Data Access 1. The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. Data transfer from empty area to CPU: Unpredictable data is transferred. 2. Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 46 Access Word Byte States H'0000 H'002F H'0030 Interrupt vector area (48 bytes) 2 On-chip ROM H'EDFF Reserved -- -- -- H'F770 Internal I/O registers (16 bytes) H'F77F H'F780 On-chip RAM H'FF7F H'FF80 H'FF9F H'FFA0 Internal I/O registers (96 bytes) H'FFFF Notes: The H8/3657 is shown as an example. * Internal I/O registers in areas assigned to timer X (H'F770 to H'F77F), SCI3 (H'FFA8 to H'FFAD), and timer V (H'FFB8 to H'FFBD) are accessed in three states. 2 or 3*2 Reserved -- -- -- 2 kbytes 2 3* Figure 2-17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules 47 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write-only bits, and when the instruction accesses an I/O port. Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address 1. Bit manipulation in two registers assigned to the same address Example 1: timer load register and timer counter Figure 2-18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. R Count clock Timer counter R: Read W: Write W Timer load register Reload Internal data bus Figure 2-18 Timer Configuration Example 48 Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output. [A: Prior to executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BSET instruction executed] BSET #0 , @PDR3 The BSET instruction is executed designating port 3. [C: After executing BSET] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 0 P36 Input High level 0 1 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output High level 1 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 3. Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input). P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU writes this value (H'41) to PDR3, completing execution of BSET. 49 As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal. However, bits 7 and 6 of PDR3 end up with different values. To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B MOV. B MOV. B #80, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR3 P36 Input High level 0 0 0 The PDR3 value (H'80) is written to a work area in memory (RAM0) as well as to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output Low level 1 0 0 [B: BSET instruction executed] BSET #0 , @RAM0 The BSET instruction is executed designating the PDR3 work area (RAM0). 50 [C: After executing BSET] MOV. B MOV. B @RAM0, R0L R0L, @PDR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 1 P36 Input High level 0 0 0 The work area (RAM0) value is written to PDR3. P35 Output Low level 1 0 0 P34 Output Low level 1 0 0 P33 Output Low level 1 0 0 P32 Output Low level 1 0 0 P31 Output Low level 1 0 0 P30 Output High level 1 1 1 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P37 Input/output Pin state PCR3 PDR3 Input Low level 0 1 P36 Input High level 0 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Output Low level 1 0 [B: BCLR instruction executed] BCLR #0 , @PCR3 The BCLR instruction is executed designating PCR3. 51 [C: After executing BCLR] P37 Input/output Pin state PCR3 PDR3 Output Low level 1 1 P36 Output High level 1 0 P35 Output Low level 1 0 P34 Output Low level 1 0 P33 Output Low level 1 0 P32 Output Low level 1 0 P31 Output Low level 1 0 P30 Input High level 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR3 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7 and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B MOV. B MOV. B #3F, R0L, R0L, P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 R0L @RAM0 @PCR3 P36 Input High level 0 0 0 The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output Low level 1 0 1 52 [B: BCLR instruction executed] BCLR #0 , @RAM0 The BCLR instruction is executed designating the PCR3 work area (RAM0). [C: After executing BCLR] MOV. B MOV. B @RAM0, R0L R0L, @PCR3 P37 Input/output Pin state PCR3 PDR3 RAM0 Input Low level 0 1 0 P36 Input High level 0 0 0 The work area (RAM0) value is written to PCR3. P35 Output Low level 1 0 1 P34 Output Low level 1 0 1 P33 Output Low level 1 0 1 P32 Output Low level 1 0 1 P31 Output Low level 1 0 1 P30 Output High level 0 0 0 Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that contain write-only bits. Table 2-12 Registers with Shared Addresses Register Name Output compare register AH and output compare register BH (timer X) Output compare register AL and output compare register BL (timer X) Timer counter B1 and timer load register B1 Port data register 1* Port data register 2* Port data register 3* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register 9* Note: * Port data registers have the same addresses as input pins. Abbreviation Address OCRAH/OCRBH H'F774 OCRAL/OCRBL H'F775 H'FFB3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC (timer B1) TCB1/TLB1 PDR1 PDR2 PDR3 PDR5 PDR6 PDR7 PDR8 PDR9 53 Table 2-13 Registers with Write-Only Bits Register Name Port control register 1 Port control register 2 Port control register 3 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register 9 PWM control register PWM data register U PWM data register L Abbreviation PCR1 PCR2 PCR3 PCR5 PCR6 PCR7 PCR8 PCR9 PWCR PWDRU PWDRL Address H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFD0 H'FFD1 H'FFD2 2.9.3 Notes on Use of the EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 R5 + R4L H'FFFF Not allowed R6 + R4L 54 Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3657 Series when a reset or interrupt occurs. Table 3-1 shows the priorities of these two types of exception handling. Table 3-1 Exception Handling Types and Priorities Priority High Exception Source Reset Interrupt Low Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 Reset 3.2.1 Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence 1. Reset by RES pin As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state. To make sure the chip is reset properly, observe the following precautions. * * * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. At power on, when using an external clock: Hold the RES pin low for the ceramic oscillator oscillation stabilization time shown in table 13.7 in the Electrical Characteristics section. Resetting during operation: Hold the RES pin low for at least 18 system clock cycles. Reset exception handling begins when the RES pin is held low for a given period, then returned to the high level. Reset exception handling takes place as follows. * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. * 55 When system power is turned on or off, the RES pin should be held low. Figure 3-1 shows the reset sequence starting from RES input. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES o Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3-1 Reset Sequence 2. Reset by watchdog timer The watchdog timer counter (TCW) starts counting up when the WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows, the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling begins. The same reset exception handling is carried out as for input at the RES pin. For details on the watchdog timer, see 9.11, Watchdog Timer. 56 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP). 3.3 Interrupts 3.3.1 Overview The interrupt sources include 12 external interrupts (IRQ3 to IRQ0, INT7 to INT0) and 21 internal interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1, interrupt request flags can be set but the interrupts are not accepted. IRQ3 to IRQ0 and INT7 to INT0 can be set independently to either rising edge sensing or falling edge sensing. * 57 Table 3-2 Interrupt Sources and Their Priorities Interrupt Source RES IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Timer A Timer B1 Timer X Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Timer A overflow Timer B1 overflow Timer X input capture A Timer X input capture B Timer X input capture C Timer X input capture D Timer X compare match A Timer X compare match B Timer X overflow Timer V Timer V compare match A Timer V compare match B Timer V overflow SCI1 SCI3 SCI1 transfer complete SCI3 transmit end SCI3 transmit data empty SCI3 receive data full SCI3 overflow error SCI3 framing error SCI3 parity error A/D (SLEEP instruction executed) A/D conversion end Direct transfer 22 23 H'002C to H'002D H'002E to H'002F Low 19 21 H'0026 to H'0027 H'002A to H'002B 17 H'0022 to H'0023 10 11 16 H'0014 to H'0015 H'0016 to H'0017 H'0020 to H'0021 Vector Number 0 4 5 6 7 8 Vector Address H'0000 to H'0001 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 Priority High Note: * Vector addresses H'0002 to H'0005, H'0024 to H'0025, H'0028 to H'0029 are reserved and cannot be used. 58 3.3.2 Interrupt Control Registers Table 3-3 lists the registers that control interrupts. Table 3-3 Interrupt Control Registers Name Interrupt edge select register 1 Interrupt edge select register 2 Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Abbreviation IEGR1 IEGR2 IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 R/W R/W R/W R/W R/W R/W R/W* R/W* R/W* Initial Value H'70 H'00 H'10 H'00 H'00 H'10 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 Note: * Write is enabled only for writing of 0 to clear a flag. 1. Interrupt edge select register 1 (IEGR1) Bit Initial value Read/Write 7 -- 0 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W IEGR1 is an 8-bit read/write register used to designate whether pins IRQ3 to IRQ0 are set to rising edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70. Bit 7: Reserved bit Bit 7 is reserved: it is always read as 0 and cannot be modified. Bits 6 to 4: Reserved bits Bits 6 to 4 are reserved; they are always read as 1, and cannot be modified. 59 Bit 3: IRQ3 edge select (IEG3) Bit 3 selects the input sensing of pin IRQ3. Bit 3 IEG3 0 1 Description Falling edge of IRQ3 pin input is detected Rising edge of IRQ3 pin input is detected (initial value) Bit 2: IRQ2 edge select (IEG2) Bit 2 selects the input sensing of pin IRQ2. Bit 2 IEG2 0 1 Description Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected (initial value) Bit 1: IRQ1 edge select (IEG1) Bit 1 selects the input sensing of pin IRQ1. Bit 1 IEG1 0 1 Description Falling edge of IRQ1 pin input is detected Rising edge of IRQ1 pin input is detected (initial value) Bit 0: IRQ0 edge select (IEG0) Bit 0 selects the input sensing of pin IRQ0. Bit 0 IEG0 0 1 Description Falling edge of IRQ0 pin input is detected Rising edge of IRQ0 pin input is detected (initial value) 60 2. Interrupt edge select register 2 (IEGR2) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 IEGR2 is an 8-bit read/write register, used to designate whether pins INT7 to INT0, TMIY, and TMIB are set to rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'00. Bit 7: INT7 edge select (INTEG7) Bit 7 selects the input sensing of the INT7 pin and TMIY pin. Bit 7 INTEG7 0 1 Description Falling edge of INT7 and TMIY pin input is detected Rising edge of INT7 and TMIY pin input is detected (initial value) Bit 6: INT6 edge select (INTEG6) Bit 6 selects the input sensing of the INT6 pin and TMIB pin. Bit 6 INTEG6 0 1 Description Falling edge of INT6 and TMIB pin input is detected Rising edge of INT6 and TMIB pin input is detected (initial value) Bit 5: INT5 edge select (INTEG5) Bit 5 selects the input sensing of the INT5 pin and ADTRG pin. Bit 5 INTEG5 0 1 Description Falling edge of INT5 and ADTRG pin input is detected Rising edge of INT5 and ADTRG pin input is detected (initial value) 61 Bits 4 to 0: INT4 to INT0 edge select (INTEG4 to INTEG0) Bits 4 to 0 select the input sensing of pins INT4 to INT0. Bit n INTEGn 0 1 Description Falling edge of INTn pin input is detected Rising edge of INTn pin input is detected (n = 4 to 0) (initial value) 3. Interrupt enable register 1 (IENR1) Bit Initial value Read/Write 7 IENTB1 0 R/W 6 IENTA 0 R/W 5 -- 0 -- 4 -- 1 -- 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1 is initialized to H'10. Bit 7: Timer B1 interrupt enable (IENTB1) Bit 7 enables or disables timer B1 overflow interrupt requests. Bit 7 IENTB1 0 1 Description Disables timer B1 interrupt requests Enables timer B1 interrupt requests (initial value) Bit 6: Timer A interrupt enable (IENTA) Bit 6 enables or disables timer A overflow interrupt requests. Bit 6 IENTA 0 1 Description Disables timer A interrupt requests Enables timer A interrupt requests (initial value) 62 Bit 5: Reserved bit Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: IRQ3 to IRQ0 interrupt enable (IEN3 to IEN0) Bits 3 to 0 enable or disable IRQ3 to IRQ0 interrupt requests. Bit n IENn 0 1 Description Disables interrupt requests from pin IRQn Enables interrupt requests from pin IRQn (n = 3 to 0) (initial value) 4. Interrupt enable register 2 (IENR2) Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 -- 4 IENS1 0 R/W 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2 is initialized to H'00. Bit 7: Direct transfer interrupt enable (IENDT) Bit 7 enables or disables direct transfer interrupt requests. Bit 7 IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value) 63 Bit 6: A/D converter interrupt enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value) Bit 5: Reserved bit Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4: SCI1 interrupt enable (IENS1) Bit 4 enables or disables SCI1 transfer complete interrupt requests. Bit 4 IENS1 0 1 Description Disables SCI1 interrupt requests Enables SCI1 interrupt requests (initial value) Bits 3 to 0: Reserved bits Bits 3 to 0 are reserved: they are always read as 0 and cannot be modified. 64 5. Interrupt enable register 3 (IENR3) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 IENR3 is an 8-bit read/write register that enables or disables INT7 to INT0 interrupt requests. Upon reset, IENR3 is initialized to H'00. Bits 7 to 0: INT7 to INT0 interrupt enable (INTEN7 to INTEN0) Bits 7 to 0 enable or disable INT7 to INT0 interrupt requests. Bit n INTENn 0 1 Description Disables interrupt requests from pin INTn Enables interrupt requests from pin INTn (n = 7 to 0) (initial value) 6. Interrupt request register 1 (IRR1) Bit Initial value Read/Write 7 IRRTB1 0 R/W * 6 IRRTA 0 R/W * 5 -- 0 -- 4 -- 1 -- 3 IRRI3 0 R/W * 2 IRRI2 0 R/W * 1 IRRI1 0 R/W * 0 IRRI0 0 R/W * Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer B1, timer A, timer Y, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is initialized to H'10. Bit 7: Timer B1 interrupt request flag (IRRTB1) Bit 7 IRRTB1 0 1 Description Clearing conditions: When IRRTB1 = 1, it is cleared by writing 0 Setting conditions: When the timer B1 counter value overflows from H'FF to H'00 (initial value) 65 Bit 6: Timer A interrupt request flag (IRRTA) Bit 6 IRRTA 0 1 Description Clearing conditions: When IRRTA = 1, it is cleared by writing 0 Setting conditions: When the timer A counter value overflows from H'FF to H'00 (initial value) Bit 5: Reserved bit Bit 5 is reserved: it is always read as 0 and cannot be modified. Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: IRQ3 to IRQ0 interrupt request flags (IRRI3 to IRRI0) Bit n IRRIn 0 1 Description Clearing conditions: When IRRIn = 1, it is cleared by writing 0 (initial value) Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 3 to 0) 66 7. Interrupt request register 2 (IRR2) Bit Initial value Read/Write 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 -- 0 -- 4 IRRS1 0 R/W * 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is initialized to H'00. Bit 7: Direct transfer interrupt request flag (IRRDT) Bit 7 IRRDT 0 1 Description Clearing conditions: When IRRDT = 1, it is cleared by writing 0 (initial value) Setting conditions: When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in SYSCR2 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD 0 1 Description Clearing conditions: When IRRAD = 1, it is cleared by writing 0 Setting conditions: When A/D conversion is completed and ADSF is cleared to 0 in ADSR (initial value) Bit 5: Reserved bit Bit 5 is reserved: it is always read as 0 and cannot be modified. 67 Bit 4: SCI1 interrupt request flag (IRRS1) Bit 4 IRRS1 0 1 Description Clearing conditions: When IRRS1 = 1, it is cleared by writing 0 Setting conditions: When an SCI1 transfer is completed (initial value) Bits 3 to 0: Reserved bits Bits 3 to 0 are reserved: they are always read as 0 and cannot be modified. 8. Interrupt request register 3 (IRR3) Bit Initial value Read/Write 7 INTF7 0 R/W * 6 INTF6 0 R/W * 5 INTF5 0 R/W * 4 INTF4 0 R/W * 3 INTF3 0 R/W * 2 INTF2 0 R/W * 1 INTF1 0 R/W * 0 INTF0 0 R/W * Note: * Only a write of 0 for flag clearing is possible IRR3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin INT7 to INT0. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR3 is initialized to H'00. Bits 7 to 0: INT7 to INT0 interrupt request flags (INTF7 to INTF0) Bit n INTFn 0 1 Description Clearing conditions: When INTFn = 1, it is cleared by writing 0 Setting conditions: When the designated signal edge is input at pin INTn (n = 7 to 0) (initial value) 3.3.3 External Interrupts There are 12 external interrupts: IRQ3 to IRQ0 and INT7 to INT0. 1. Interrupts IRQ3 to IRQ0 Interrupts IRQ3 to IRQ0 are requested by input signals to pins IRQ3 to IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1. 68 When these pins are designated as pins IRQ3 to IRQ0 in port mode register 1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits IEN3 to IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR. When IRQ3 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector numbers 7 to 4 are assigned to interrupts IRQ3 to IRQ0. The order of priority is from IRQ0 (high) to IRQ3 (low). Table 3-2 gives details. 2. INT interrupts INT interrupts are requested by input signals to pins INT7 to INT0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits INTEG7 to INTEG0 in IEGR2. When the designated edge is input at pins INT7 to INT0, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits INTEN7 to INTEN0 to 0 in IENR3. These interrupts can all be masked by setting the I bit to 1 in CCR. When INT interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector number 8 is assigned to the INT interrupts. All eight interrupts have the same vector number, so the interrupthandling routine must discriminate the interrupt source. Note: Pins INT7 to INT0 are multiplexed with port 5. Even in port usage of these pins, whenever the designated edge is input or output, the corresponding bit INTFn is set to 1. 3.3.4 Internal Interrupts There are 21 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 23 to 9 are assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from on-chip peripheral modules. 69 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Priority decision logic Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3-2 Block Diagram of Interrupt Controller Interrupt operation is described as follows. * When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. When the interrupt controller receives an interrupt request, it sets the interrupt request flag. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3-2 for a list of interrupt priorities.) The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. * * * 70 * If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. The I bit of CCR is set to 1, masking further interrupts. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. * * Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 2. 71 Program execution state IRRIO = 1 Yes IENO = 1 Yes No No No IRRI1 = 1 Yes IEN1 = 1 Yes No No IRRI2 = 1 Yes IEN2 = 1 Yes No IRRDT = 1 Yes IENDT = 1 Yes No No No I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine Notation: PC: Program counter CCR: Condition code register I: I bit of CCR Figure 3-3 Flow up to Interrupt Acceptance 72 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR PCH PCL Even address Prior to start of interrupt exception handling Notation: PCH: Upper 8 bits of program counter (PC) Lower 8 bits of program counter (PC) PCL: CCR: Condition code register Stack pointer SP: PC and CCR saved to stack After completion of interrupt exception handling Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word access, starting from an even-numbered address. Figure 3-4 Stack State after Completion of Interrupt Exception Handling Figure 3-5 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. 73 Interrupt is accepted Interrupt level decision and wait for end of instruction Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing Interrupt request signal o Internal address bus (1) (3) (5) (6) (8) (9) Figure 3-5 Interrupt Sequence 74 (2) (4) (1) (7) Internal read signal Internal write signal (9) (10) Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector address.) (10) First instruction of interrupt-handling routine 3.3.6 Interrupt Response Time Table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3-4 Interrupt Wait States Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Total Note: * Not including EEPMOV instruction. States 1 to 13 4 2 4 4 15 to 27 75 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the H8/3657 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-6. SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP Notation: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3-6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. 76 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ3 to IRQ1, the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Table 3-5 shows the conditions under which interrupt request flags are set to 1 in this way. Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 IRR1 IRRI3 Conditions When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. Be sure to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur. 77 CCR I bit 1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3-7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 78 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4-1 shows a block diagram of the clock pulse generators. OSC 1 OSC 2 System clock oscillator o OSC (f OSC) oOSC/2 System clock divider (1/2) oOSC/128 System clock o OSC/64 divider (1/64, 1/32, oOSC/32 1/16, 1/8) oOSC/16 oW /2 oW /4 oW /8 o Prescaler S (13 bits) o/2 to o/8192 System clock pulse generator X1 X2 Subclock oscillator oW (f W ) Subclock divider (1/2, 1/4, 1/8) oSUB oW /2 oW /4 oW /8 to oW /128 Subclock pulse generator Prescaler W (5 bits) Figure 4-1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock The basic clock signals that drive the CPU and on-chip peripheral modules are o and oSUB. Four of the clock signals have names: o is the system clock, oSUB is the subclock, oOSC is the oscillator clock, and oW is the watch clock. The clock signals available for use by peripheral modules are o/2, o/4, o/8, o/16, o/32, o/64, o/128, o/256, o/512, o/1024, o/2048, o/4096, o/8192, oW/2, oW/4, oW/8, oW/16, oW/32, oW/64, and oW/128. The clock requirements differ from one module to another. 79 4.2 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. Connecting a crystal oscillator Figure 4-2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = C 2 = 12 pF 20% Figure 4-2 Typical Connection to Crystal Oscillator Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4-1 should be used. CS LS OSC 1 RS OSC 2 C0 Figure 4-3 Equivalent Circuit of Crystal Oscillator Table 4-1 Crystal Oscillator Parameters Frequency (MHz) RS max () C0 (pF) 2 500 7 pF max 4 100 8 50 10 30 80 2. Connecting a ceramic oscillator Figure 4-4 shows a typical method of connecting a ceramic oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = 30 pF 10% C2 = 30 pF 10% Ceramic oscillator: Murata Figure 4-4 Typical Connection to Ceramic Oscillator 3. Notes on board design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4-5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C2 OSC 1 OSC 2 C1 Figure 4-5 Board Design of Oscillator Circuit 81 4. External clock input method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4-6 shows a typical connection. OSC 1 OSC 2 External clock input Open Figure 4-6 External Clock Input (Example) Frequency Duty cycle Oscillator Clock (oOSC) 45% to 55% 82 4.3 Subclock Generator 1. Connecting a 32.768-kHz crystal oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4-7. Follow the same precautions as noted under 4.2.3, Note on board design, for the system clock. C1 X1 X2 C2 C1 = C 2 = 15 pF (typ.) Figure 4-7 Typical Connection to 32.768-kHz Crystal Oscillator Figure 4-8 shows the equivalent circuit of the 32.768-kHz crystal oscillator. CS LS X1 RS X2 C0 C0 = 1.5 pF typ RS = 14 k typ f W = 32.768 kHz Crystal oscillator: MX38T (Nihon Denpa Kogyo) Figure 4-8 Equivalent Circuit of 32.768-kHz Crystal Oscillator 83 2. Pin connection when not using subclock When the subclock is not used, connect pin X1 to VCC and leave pin X2 open, as shown in figure 4-9. VCC X1 X2 Open Figure 4-9 Pin Connection when not Using Subclock 84 4.4 Prescalers The H8/3657 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (o) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5bit counter using a 32.768-kHz signal divided by 4 (oW/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. 1. Prescaler S (PSS) Prescaler S is a 13-bit counter using the system clock (o) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is determined by the division factor designated by MA1 and MA0. 2. Prescaler W (PSW) Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (oW/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping. 85 4.5 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user for both mask ROM and ZTATTM versions, referring to the oscillator element connection examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 86 Section 5 Power-Down Modes 5.1 Overview The H8/3657 Series has eight modes of operation after a reset. These include seven power-down modes, in which power dissipation is significantly reduced. Table 5-1 gives a summary of the eight operating modes. Table 5-1 Operating Modes Operating Mode Active (high-speed) mode Active (medium-speed) mode Description The CPU and all on-chip peripheral functions are operable on the system clock The CPU and all on-chip peripheral functions are operable on the system clock, but at 1/64, 1/32, 1/6, or 1/8* the speed in active (high-speed) mode The CPU, and the time-base function of timer A are operable on the subclock The CPU halts. On-chip peripheral functions except PWM are operable on the system clock The CPU halts. On-chip peripheral functions except PWM are operable on the system clock, but at 1/64, 1/32, 1/6, or 1/8* the speed in active (high-speed) mode The CPU halts. The time-base function of timer A are operable on the subclock The CPU halts. The time-base function of timer A is operable on the subclock The CPU and all on-chip peripheral functions halt Subactive mode Sleep (high-speed) mode Sleep (medium-speed) mode Subsleep mode Watch mode Standby mode Note: * Determined by the value set in bits MA1 and MA0 of system control register 1 (SYSCR1). Of these eight operating modes, all but the active (high-speed) mode are power-down modes. In this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode, and the two sleep modes (high-speed and medium speed) will be referred to collectively as sleep mode. 87 Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal states in each mode. Reset state Program execution state Active (high-speed) mode SLEEP instruction*g SLEEP instruction*f SLEEP instruction*a *3 a Program halt state Sleep (high-speed) mode Program halt state P EE n SL uctio tr ins *4 *d Standby mode SL instr EEP uctio *d n *4 P* EE tion SL ruc st inin SL st E ru EP ct io n* b ins SLEE tru ctio P n *e Active (medium-speed) mode SLEEP instruction*h SLEEP instruction*i *e EP n LE ctio S ru st in SLEEP instruction*b *3 Sleep (medium-speed) mode *1 *1 Watch mode SLEEP instruction*e *1 Subactive mode ins SLEE tru P cti on * j SL ins E tru EP ctio n *i SLEEP instruction*c *2 Subsleep mode Power-down modes Mode Transition Conditions (1) LSON MSON SSBY TMA3 DTON a b c d e f g h i J 0 0 1 0 T 0 0 0 1 0 0 1 T T T 0 1 1 T 0 0 0 0 1 1 0 0 1 1 1 T T 1 0 1 T T 1 1 1 0 0 0 0 0 1 1 1 1 1 1 2 3 4 Mode Transition Conditions (2) Interrupt Sources Timer A interrupt, IRQ0 interrupt Timer A interrupt, IRQ3 to IRQ0 interrupts, INT interrupt All interrupts IRQ1 or IRQ0 interrupt T Don't care Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that interrupt handling is performed after the interrupt is accepted. 2. Details on the mode transition conditions are given in the explanations of each mode, in sections 5-2 through 5-8. Figure 5-1 Mode Transition Diagram 88 Table 5-2 Internal State in Each Operating Mode Active Mode Function System clock oscillator Subclock oscillator CPU operations Instructions Registers RAM I/O ports External interrupts IRQ0 IRQ1 IRQ2 IRQ3 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Peripheral functions Timer A Timer B1 Timer V Timer X Watchdog timer SCI1 SCI3 PWM A/D converter Retained Functions Retained Functions Reset Retained Reset Retained Reset Retained Reset Retained Retained Retained Retained Retained Functions Functions Functions Functions Functions*3 Functions*3 Functions*3 Retained Retained Reset Retained Reset Retained Reset Reset Functions Functions Functions Functions Retained*2 Functions Functions Retained*2 Functions Functions Functions Functions Functions Retained*2 Retained*2 Functions Functions Retained*1 Functions HighSpeed Functions Functions Functions MediumSpeed Functions Functions Functions Sleep Mode HighSpeed Functions Functions Halted Retained MediumSpeed Functions Functions Halted Retained Watch Mode Halted Functions Halted Retained Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained Standby Mode Halted Functions Halted Retained Notes: 1. Register contents are retained, but output is high-impedance state. 2. External interrupt requests are ignored. Interrupt request register contents are not altered. 3. Functions if timekeeping time-base function is selected. 89 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5-3. Table 5-3 System Control Registers Name System control register 1 System control register 2 Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'E0 Address H'FFF0 H'FFF1 1. System control register 1 (SYSCR1) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 -- 1 -- 1 MA1 1 R/W 0 MA0 1 R/W SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'07. Bit 7: Software standby (SSBY) This bit designates transition to standby mode or watch mode. Bit 7 SSBY 0 Description * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode (initial value) * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode 90 Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms. Bit 6 STS2 0 0 0 0 1 Bit 5 STS1 0 0 1 1 * Bit 4 STS0 0 1 0 1 * Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states (initial value) Note: * Don't care Bit 3: Low speed on flag (LSON) This bit chooses the system clock (o) or subclock (oSUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON 0 1 Description The CPU operates on the system clock (o) The CPU operates on the subclock (oSUB) (initial value) Bits 2: Reserved bits Bit 2 is reserved: it is always read as 1 and cannot be modified. Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0) Bits 1 and 0 choose oosc/128, oosc/64, oosc/32, or oosc/16 as the operating clock in active (mediumspeed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (highspeed) mode or subactive mode. Bit 1 MA1 0 0 1 1 Bit 0 MA0 0 1 0 1 Description oosc/16 oosc/32 oosc/64 oosc/128 (initial value) 91 2. System control register 2 (SYSCR2) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5: Reserved bits These bits are reserved; they are always read as 1, and cannot be modified. Bit 4: Noise elimination sampling frequency select (NESEL) This bit selects the frequency at which the watch clock signal (oW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (oOSC) generated by the system clock pulse generator. When oOSC = 2 to 10 MHz, clear NESEL to 0. Bit 4 NESEL 0 1 Description Sampling rate is oOSC/16 Sampling rate is oOSC/4 (initial value) 92 Bit 3: Direct transfer on flag (DTON) This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits. Bit 3 DTON 0 Description * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode (initial value) * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 * When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Bit 2: Medium speed on flag (MSON) After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or sleep (highspeed) mode, and active (medium speed) or sleep (medium-speed) mode. Bit 2 MSON 0 Description * After standby, watch, or sleep mode is cleared, operation is in active (high-speed) mode * When a SLEEP instruction is executed in active mode, a transition is made to sleep (high-speed) mode * After standby, watch, or sleep mode is cleared, operation is in active (medium-speed) mode * When a SLEEP instruction is executed in active mode, a transition is made to sleep (medium-speed) mode 1 93 Bits 1 and 0: Subactive mode clock select (SA1 and SA0) These bits select the CPU clock rate (oW/2, oW/4, or oW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 0 0 1 Bit 0 SA0 0 1 * Description oW/8 oW/4 oW/2 (initial value) Note: * Don't care 94 5.2 Sleep Mode 5.2.1 Transition to Sleep Mode 1. Transition to sleep (high-speed) mode The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 and the MSON and DTON bits in SYSCR2 are all cleared to 0. In sleep (high-speed) mode CPU operation is halted but the on-chip peripheral functions other than PWM are operational. CPU register contents are retained. 2. Transition to sleep (medium-speed) mode The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions other than PWM are operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained. 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer B1, timer X, timer V, IRQ3 to IRQ0, INT7 to INT0, SCI3, SCI1, or A/D converter), or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 95 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ1 or IRQ0) or by input at the RES pin. * Clearing by interrupt When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2-STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (highspeed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 96 5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. * When a crystal oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. * When an external clock is used Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. Table 5-3 Clock Frequency and Settling Time (times are in ms) STS2 0 0 0 0 1 STS1 0 0 1 1 * STS0 0 1 0 1 * Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 5 MHz 1.6 3.2 6.6 13.1 26.2 4 MHz 2.0 4.1 8.2 16.4 32.8 2 MHz 4.1 8.2 16.4 32.8 65.5 1 MHz 8.2 16.4 32.8 65.5 131.1 0.5 MHz 16.4 32.8 65.5 131.1 262.1 Note: * Don't care 97 5.4 Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before the transition. 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A or IRQ0) or by a low input at the RES pin. * Clearing by interrupt When watch mode is cleared by a timer A interrupt or IRQ0 interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2-STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode is Cleared The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after Standby Mode is Cleared. 98 5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A and timer C is halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, IRQ3 to IRQ0, INT7 to INT0) or by a low input at the RES pin. * Clearing by interrupt When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. * Clearing by RES input Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 99 5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A or IRQ0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, IRQ3 to IRQ0, or INT7 to INT0 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin. * Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer. * Clearing by RES pin Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are oW/2, oW/4, and oW/8. 100 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the LSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0 or IRQ1 interrupts in standby mode, timer A or IRQ0 interrupts in watch mode, or any interrupt in sleep (medium-speed) mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (Medium-Speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction or by a low input at the RES pin. * Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed, sleep (high-speed) mode is entered if MSON is cleared to 0 in SYSCR2, and sleep (medium-speed) mode is entered if MSON is set to 1. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See 5.8, Direct Transfer, below for details. * Clearing by RES pin When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (Medium-Speed) Mode Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. 101 5.8 Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. * Direct transfer from active (high-speed) mode to active (medium-speed) mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. * Direct transfer from active (medium-speed) mode to active (high-speed) mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. * Direct transfer from active (high-speed) mode to subactive mode When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (high-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 102 * Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode. * Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 103 Section 6 ROM 6.1 Overview The H8/3657 has 60 kbytes of on-chip mask ROM or PROM. The H8/3656 has 48 kbytes of mask ROM. The H8/3655 has 40 kbytes of mask ROM. The H8/3654 has 32 kbytes of on-chip mask ROM. The H8/3653 has 24 kbytes of mask ROM. The H8/3652 has 16 kbytes of mask ROM. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. 6.1.1 Block Diagram Figure 6-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'EDFE H'EDFE Even-numbered address H'EDFF Odd-numbered address Figure 6-1 ROM Block Diagram (H8/3657) 105 6.2 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. Table 6-1 shows how to set the chip to PROM mode. Table 6-1 Setting to PROM Mode Pin Name TEST PB4/AN4 PB5/AN5 PB6/AN6 High level Setting High level Low level 6.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins, as listed in table 6-2. Figure 6-2 shows the pin-to-pin wiring of the socket adapter. Figure 6-3 shows a memory map. Table 6-2 Socket Adapter Package 80-pin (TFP-80F) 80-pin (TFP-80C) 80-pin (FP-80A) 80-pin (FP-80B) Socket Adapter 106 H8/3657 TFP-80C, TFP-80F FP-80A 12 28 29 30 31 32 33 34 35 51 50 49 48 47 46 45 44 73 19 75 39 40 41 42 54 55 43 74 62 13, 53 76 6 8 78 60 61 56 9, 52 5 80 79 EPROM socket FP-80B 14 30 31 32 33 34 35 36 37 53 52 51 50 49 48 47 46 75 21 77 41 42 43 44 56 57 45 76 64 15, 55 78 8 10 80 62 63 58 11, 54 7 2 1 Pin RES P60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P15 IRQ 0 P17 P73 P74 P75 P76 P30 P3 1 P77 P16 P22 VCC AVCC TEST X1 PB6 P20 P21 P32 VSS AVSS PB4 PB5 Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC HN27CI01 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 VSS 16 Note: Pins not indicated in the figure should be left open. Figure 6-2 Socket Adapter Pin Correspondence (with HN27C101) 107 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'EDFF H'EDFF Missing area * H'1FFFF Note: * If read in PROM mode, this address area returns unpredictable output data. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become impossible to program the PROM or verify the programmed data. When programming, assign H'FF data to this address area (H'EE00 to H'1FFFF). Figure 6-3 Memory Map in PROM Mode 108 6.3 Programming The write, verify, and other modes are selected as shown in table 6-3 in H8/3657 PROM mode. Table 6-3 Mode Selection in H8/3657 PROM Mode Pin Mode Write Verify Programming disabled CE L L L L H H Notation L: Low level H: High level VPP: VPP level VCC: VCC level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input The specifications for writing and reading the on-chip PROM are identical to those for the standard HN27C101 EPROM. Page programming is not supported, however. The PROM writer must not be set to page mode. A PROM programmer that provides only page programming mode cannot be used. When selecting a PROM programer, check that it supports a byte-by-byte high-speed, highreliability programming method. Be sure to set the address range to H'0000 to H'EDFF. 6.3.1 Writing and Verifying An efficient, high-speed, high-reliability method is available for writing and verifying the PROM data. This method achieves high speed without voltage stress on the device and without lowering the reliability of written data. The basic flow of this high-speed, high-reliability programming method is shown in figure 6-4. 109 Start Set write/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n+1 n No Yes n < 25 Write time t PW = 0.2 ms 5% No Go Verify Go Write time t OPW = 0.2n ms No Address + 1 address Last address? Yes Set read mode VCC = 5.0 V 0.25 V, V PP = VCC No Error All addresses read? Yes End Figure 6-4 High-Speed, High-Reliability Programming Flow Chart 110 Table 6-4 and table 6-5 give the electrical characteristics in programming mode. Table 6-4 DC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage EO7 to EO0, EA16 to EA0 OE, CE, PGM EO7 to EO0, EA16 to EA0 OE, CE, PGM EO7 to EO0 EO7 to EO0 Symbol VIH VIL VOH VOL |ILI| ICC IPP Min 2.4 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max Test Unit Conditions VCC + 0.3 V 0.8 -- 0.45 2 40 40 V V V A mA mA IOH = -200 A IOL = 0.8 mA Vin = 5.25 V/ 0.5 V Input leakage EO7 to EO0, EA16 to EA0 current OE, CE, PGM VCC current VPP current 111 Table 6-5 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width PGM pulse width for overwrite programming VCC setup time CE setup time Data output delay time Symbol tAS tOES tDS tAH tDH tDF*2 tVPS tPW tOPW*3 tVCS tCES tOE Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 200 Unit s s s s s ns s ms ms s s ns Test Conditions Figure 6-5*1 Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time 20 ns Timing reference levels Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. tDF is defined at the point at which the output is floating and the output level cannot be read. 3. tOPW is defined by the value given in figure 6-4 high-speed, high-reliability programming flow chart. 112 Figure 6-5 shows a write/verify timing diagram. Write Address tAS Data tDS VPP VPP VCC VCC +1 VCC tVCS tVPS Input data tDH Verify tAH Output data tDF VCC CE tCES PGM tPW OE tOPW* tOES tOE Note: * tOPW is defined by the value given in figure 6-4 high-speed, high-reliability programming flow chart. Figure 6-5 PROM Write/Verify Timing 113 6.3.2 Programming Precautions * Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. Select the programming mode carefully. The chip cannot be programmed in page programming mode. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become impossible to program the PROM or verify the programmed data. When programming, assign H'FF data to the address area from H'EE00 to H'1FFFF. * * * 114 6.4 Reliability of Programmed Data A highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150C. This quickly eliminates PROM memory cells prone to initial data retention failure. Figure 6-6 shows a flowchart of this screening procedure. Write program and verify contents Bake at high temperature with power off 125C to 150C, 24 hrs to 48 hrs Read and check program Install Figure 6-6 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 115 Section 7 RAM 7.1 Overview The H8/3657 Series has 1 kbyte or 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'E780 H'F782 H'F780 H'F782 H'F781 H'F783 On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address Figure 7-1 RAM Block Diagram (Example of 2 kbytes ROM) 117 Section 8 I/O Ports 8.1 Overview The H8/3657 Series is provided with six 8-bit I/O ports, one 6-bit I/O port, one 5-bit I/O ports, and one 8-bit input-only port. Table 8-1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in Appendix C. Table 8-1 Port Functions Function Switching Register PMR1 Port Port 1 Description Pins Other Functions External interrupt 3, timer V trigger input External interrupts 2 and 1 14-bit PWM output * 8-bit I/O port P17/IRQ3/TRGV * MOS input pull-up P16 to P15/ option IRQ2 to IRQ1 P14/PWM P13 to P11 P10/TMOW PMR1 Timer A clock output PMR1 Port 2 * 8-bit I/O port P27 to P23 P22/TXD P21/RXD P20/SCK1 SCI3 data output SCI3 data input SCI3 clock input/output PMR7 SCR3 SCR3, SMR Port 3 * 6-bit I/O port P35 to P33 * MOS input pull-up P32/SO1 option P31/SI1 P30/SCK1 * 8-bit I/O port P57 /INT7 * MOS input pull-up P56 /INT6/ TMIB P55/INT5/ ADTRG P54 to P50/ INT4 to INT0 SCI1 data output (SO1), data input (SI1), clock input/output (SCK1) INT interrupt 7 INT interrupt 6 Timer B 1 event input INT interrupt 5 A/D converter external trigger input INT interrupts 4 to 0 PMR3 Port 5 119 Table 8-1 Port Functions (cont) Function Switching Register Port Port 6 Port 7 Description * 8-bit I/O port * 8-bit I/O port Pins P67 to P60 P77 P76/TMOV P75/TMCIV P74/TMRIV P73 to P70 Other Functions Timer V compare-match output Timer V clock input Timer V reset input TCSRV Port 8 * 8-bit I/O port P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI Timer X input capture D input Timer X input capture C input Timer X input capture B input Timer X input capture A input Timer X output compare B output Timer X output compare A output Timer X clock input TOCR TOCR Port 9 Port B * 5-bit I/O port * 8-bit input port P90 to P94 PB7 to PB0/ AN7 to AN0 A/D converter analog input (AN7 to AN0) 120 8.2 Port 1 8.2.1 Overview Port 1 is a 8-bit I/O port. Figure 8-1 shows its pin configuration. P1 7 /IRQ 3 /TRGV P1 6 /IRQ 2 P1 5 /IRQ 1 Port 1 P1 4 /PWM P1 3 P1 2 P1 1 P1 0 /TMOW Figure 8-1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8-2 shows the port 1 register configuration. Table 8-2 Port 1 Registers Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1 Abbrev. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'04 Address H'FFD4 H'FFE4 H'FFED H'FFFC 121 1. Bit Port data register 1 (PDR1) 7 P1 7 0 R/W 6 P1 6 0 R/W 5 P1 5 0 R/W 4 P1 4 0 R/W 3 P13 0 R/W 2 P1 2 0 R/W 1 P11 0 R/W 0 -- 0 -- Initial value Read/Write PDR1 is an 8-bit register that stores data for port 1 pins P17 and P10. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 1 (PCR1) 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 and P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register, which is always read as all 1s. 122 3. Bit Port pull-up control register 1 (PUCR1) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 -- 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 Initial value Read/Write PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 and P10 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00. 4. Port mode register 1 (PMR1) Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 -- 0 -- 2 -- 1 -- 1 -- 0 -- 0 TMOW 0 R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'04. Bit 7: P17/IRQ3/TRGV pin function switch (IRQ3) This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. Bit 7 IRQ3 0 1 Description Functions as P17 I/O pin Functions as IRQ3/TRGV input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ3. Rising, falling, or both edge sensing can be designated for TRGV. For details on TRGV settings, see 9.8.2 (5), Timer Control Register V1 (TCRV1). 123 Bit 6: P16/IRQ2 pin function switch (IRQ2) This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2. Bit 6 IRQ2 0 1 Description Functions as P16 I/O pin Functions as IRQ2 input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ2. Bit 5: P15/IRQ1 pin function switch (IRQ1) This bit selects whether pin P15/IRQ1 is used as P15 or as IRQ1. Bit 5 IRQ1 0 1 Description Functions as P15 I/O pin Functions as IRQ1 input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1. Bit 4: P14/PWM pin function switch (PWM) This bit selects whether pin P14/PWM is used as P14 or as PWM. Bit 4 PWM 0 1 Description Functions as P14 I/O pin Functions as PWM output pin (initial value) Bit 3: Reserved bit Bit 3 is reserved: it is always read as 0 and cannot be modified. Bit 2: Reserved bit Bit 2 is reserved: it is always read as 1 and cannot be modified. Bit 1: Reserved bit Bit 1 is reserved: it is always read as 0 and cannot be modified. 124 Bit 0: P10/TMOW pin function switch (TMOW) This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0 TMOW 0 1 Description Functions as P10 I/O pin Functions as TMOW output pin (initial value) 8.2.3 Pin Functions Table 8-3 shows the port 1 pin functions. Table 8-3 Port 1 Pin Functions Pin Pin Functions and Selection Method P17/IRQ3/TRGV The pin function depends on bit IRQ3 in PMR1 and bit PCR17 in PCR1. IRQ3 PCR17 Pin function P16/IRQ2 P15/IRQ1 0 0 1 1 * IRQ3/TRGV input pin P17 input pin P17 output pin The pin function depends on bits IRQ2 and IRQ1 in PMR1 and bit PCR1n in PCR1. (m = n - 4, n = 6, 5) IRQm PCR1n Pin function 0 0 1 1 * IRQm input pin P1n input pin P1n output pin P14/PWM The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1. PWM PCR14 Pin function 0 0 1 1 * PWM output pin P14 input pin P14 output pin P13 to P11 The pin function depends on bit PCR1n in PCR1. (n = 3 to 1) PCR1n Pin function 0 P1n input pin 1 P1n output pin 125 Table 8-3 Port 1 Pin Functions (cont) Pin P10/TMOW Pin Functions and Selection Method The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1. TMOW PCR10 Pin function Note: * Don't care 0 0 1 1 * TMOW output pin P10 input pin P10 output pin 8.2.4 Pin States Table 8-4 shows the port 1 pin states in each operating mode. Table 8-4 Port 1 Pin States Pins P17/IRQ3/TRGV P16/IRQ2 P15/IRQ1 P14/PWM P13 to P11 P10/TMOW Reset Sleep Subsleep Retains previous state Standby Highimpedance* Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n PUCR1n MOS input pull-up Note: * Don't care n = 7 to 0 0 Off 0 1 On 1 * Off 126 8.3 Port 2 8.3.1 Overview Port 2 is a 8-bit I/O port, configured as shown in figure 8-2. P2 7 P2 6 P2 5 Port 2 P2 4 P2 3 P2 2 /TXD P2 1 /RXD P2 0 /SCK3 Figure 8-2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8-5 shows the port 2 register configuration. Table 8-5 Port 2 Registers Name Port data register 2 Port control register 2 Abbrev. PDR2 PCR2 R/W R/W W Initial Value H'00 H'00 Address H'FFD5 H'FFE5 1. Port data register 2 (PDR2) Bit Initial value Read/Write 7 P2 7 0 R/W 6 P2 6 0 R/W 5 P2 5 0 R/W 4 P2 4 0 R/W 3 P2 3 0 R/W 2 P2 2 0 R/W 1 P2 1 0 R/W 0 P2 0 0 R/W PDR2 is an 8-bit register that stores data for port 2 pins P27 to P20. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00. 127 2 Bit Port control register 2 (PCR2) 7 PCR2 7 0 W 6 PCR26 0 W 5 PCR2 5 0 W 4 PCR2 4 0 W 3 PCR2 3 0 W 2 PCR2 2 0 W 1 PCR2 1 0 W 0 PCR2 0 0 W Initial value Read/Write PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only when the corresponding pin is designated in SCR3 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register, which is always read as all 1s. 128 8.3.3 Pin Functions Table 8-6 shows the port 2 pin functions. Table 8-6 Port 2 Pin Functions Pin P27 to P23 Pin Functions and Selection Method The pin function depends on bit PCR2n in PCR2. (n = 7 to 3) PCR2n Pin function 0 P2n input pin 1 P2n output pin P22/TXD The pin function depends on bit TXD in PMR7 and bit PCR22 in PCR2. TXD PCR22 Pin function 0 0 1 1 * TXD output pin P22 input pin P22 output pin P21/RXD The pin function depends on bit RE in SCR3 and bit PCR21 in PCR2. RE PCR21 Pin function 0 0 1 1 * RXD input pin P21 input pin P21 output pin P20/SCK3 The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR, and bit PCR20 in PCR2. CKE1 CKE0 COM PCR20 Pin function 0 0 1 0 1 * 0 1 * 1 * * * SCK3 input pin P20 input pin P20 output pin SCK3 output pin Note: * Don't care 129 8.3.4 Pin States Table 8-7 shows the port 2 pin states in each operating mode. Table 8-7 Port 2 Pin States Pins P27 to P23 P22/TXD P21/RXD P20/SCK3 Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 130 8.4 Port 3 8.4.1 Overview Port 3 is a 6-bit I/O port, configured as shown in figure 8-3. P3 5 P3 4 Port 3 P3 3 P3 2 /SO 1 P3 1 /SI 1 P3 0 /SCK1 Figure 8-3 Port 3 Pin Configuration 8.4.2 Register Configuration and Description Table 8-8 shows the port 3 register configuration. Table 8-8 Port 3 Registers Name Port data register 3 Port control register 3 Port pull-up control register 3 Port mode register 3 Port mode register 7 Abbrev. PDR3 PCR3 PUCR3 PMR3 PMR7 R/W R/W W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'F8 Address H'FFD6 H'FFE6 H'FFEE H'FFFD H'FFFF 131 1. Bit Port data register 3 (PDR3) 7 -- 0* -- 6 -- 0* -- 5 P3 5 0 R/W 4 P3 4 0 R/W 3 P3 3 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P3 0 0 R/W Initial value Read/Write Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified. PDR3 is an 8-bit register that stores data for port 3 pins P35 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read. Upon reset, PDR3 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 3 (PCR3) 7 -- 0 -- 6 -- 0 -- 5 PCR3 5 0 W 4 PCR3 4 0 W 3 0 W 2 0 W 1 PCR31 0 W 0 PCR30 0 W PCR3 3 PCR3 2 PCR3 is an 8-bit register for controlling whether each of the port 3 pins P35 to P30 functions as an input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I/O pin. Upon reset, PCR3 is initialized to H'00. PCR3 is a write-only register, which is always read as all 1s. 132 3. Bit Port pull-up control register 3 (PUCR3) 7 -- 0* -- 6 -- 0* -- 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR35 PUCR34 PUCR33 PUCR3 2 PUCR31 PUCR30 Initial value Read/Write Note: * Bits 7 to 3 are reserved; they are always read as 0 and cannot be modified. PUCR3 controls whether the MOS pull-up of each of the port 3 pins P35 to P30 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR3 is initialized to H'00. 4. Port mode register 3 (PMR3) Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SO1 0 R/W 1 SI1 0 R/W 0 SCK1 0 R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Upon reset, PMR3 is initialized to H'00. Bits 7 to 3: Reserved bits Bits 7 to 3 are reserved: they are always read as 0 and cannot be modified. Bit 2: P32/SO1 pin function switch (SO1) This bit selects whether pin P32/SO1 is used as P32 or as SO1. Bit 2 SO1 0 1 Description Functions as P32 I/O pin Functions as SO1 output pin (initial value) 133 Bit 1: P31/SI1 pin function switch (SI1) This bit selects whether pin P31/SI1 is used as P31 or as SI1. Bit 1 SI1 0 1 Description Functions as P31 I/O pin Functions as SI1 input pin (initial value) Bit 0: P30/SCK1 pin function switch (SCK1) This bit selects whether pin P30/SCK1 is used as P30 or as SCK1. Bit 0 SCK1 0 1 Description Functions as P30 I/O pin Functions as SCK1 I/O pin (initial value) 5. Port mode register 7 (PMR7) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TXD 0 R/W 1 -- 0 -- 0 POF1 0 R/W PMR7 is an 8-bit read/write register that turns the PMOS transistors of pins and P32/SO1 on and off. Upon reset, PMR7 is initialized to H'F8. Bits 7 to 3: Reserved bits Bits 7 to 3 are reserved; they are always read as 1, and cannot be modified. Bit 2: P22/TXD pin function switch (TXD) Bit 2 selects whether pin P22/TXD is used as P22 or as TXD. Bit 2 TXD 0 1 Description Functions as P22 I/O pin Functions as TXD output pin (initial value) 134 Bit 1: Reserved bit Bit 1 is reserved: it is always read as 0 and cannot be modified. Bit 0: P32/SO1 pin PMOS control (POF1) This bit controls the PMOS transistor in the P32/SO1 pin output buffer. Bit 0 POF1 0 1 Description CMOS output NMOS open-drain output (initial value) 8.4.3 Pin Functions Table 8-9 shows the port 3 pin functions. Table 8-9 Port 3 Pin Functions Pin P35 to P33 Pin Functions and Selection Method The pin function depends on bit PCR3n in PCR3. (n = 5 to 3) PCR3n Pin function 0 P3n input pin 1 P3n output pin P32/SO1 The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3. SO1 PCR32 Pin function 0 0 1 1 * SO1 output pin P32 input pin P32 output pin P31/SI1 The pin function depends on bit SI1 in PMR3 and bit PCR31 in PCR3. SI1 PCR31 Pin function 0 0 1 1 * SI1 input pin P31 input pin P31 output pin 135 Table 8-9 Port 3 Pin Functions (cont) Pin P30/SCK1 Pin Functions and Selection Method The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit PCR30 in PCR3. SCK1 CKS3 PCR30 Pin function Note: * Don't care 0 0 * 1 0 * 1 1 * P30 input pin P30 output pin SCK1 output pin SCK1 input pin 8.4.4 Pin States Table 8-10 shows the port 3 pin states in each operating mode. Table 8-10 Port 3 Pin States Pins P35 to P33 P32/SO1 P31/SI1 P30/SCK1 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Watch Subactive Active HighRetains Functional Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.4.5 MOS Input Pull-Up Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR3n PUCR3n MOS input pull-up Note: * Don't care 0 Off 0 1 On 1 * Off (n = 5 to 0) 136 8.5 Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8-4. P57/INT7 P56/INT6/TMIB P55/INT5/ADTRG Port 5 P54/INT4 P53/INT3 P52/INT2 P51/INT1 P50/INT0 Figure 8-4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8-11 shows the port 5 register configuration. Table 8-11 Port 5 Registers Name Port data register 5 Port control register 5 Port pull-up control register 5 Abbrev. PDR5 PCR5 PUCR5 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FFEF 137 1. Port data register 5 (PDR5) Bit Initial value Read/Write 7 P5 7 0 R/W 6 P5 6 0 R/W 5 P55 0 R/W 4 P5 4 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P5 0 0 R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. 2. Port control register 5 (PCR5) Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register, which is always read as all 1s. 3. Port pull-up control register 5 (PUCR5) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. 138 8.5.3 Pin Functions Table 8-12 shows the port 5 pin functions. Table 8-12 Port 5 Pin Functions Pin P57/INT7 Pin Functions and Selection Method The pin function depends on bit PCR57 in PCR5. PCR57 Pin function 0 P57 input pin INT7 input pin 1 P57 output pin P56/INT6/TMIB The pin function depends on bit PCR56 in PCR5. PCR56 Pin function 0 P56 input pin 1 P56 output pin INT6 input pin and TMIB input pin P55/INT5/ ADTRG The pin function depends on bit PCR55 in PCR5. PCR55 Pin function 0 P55 input pin 1 P55 output pin INT5 input pin and ADTRG input pin P54/INT4 to P50/INT0 The pin function depends on bit PCR5n in PCR5. (n = 4 to 0) PCR5n Pin function 0 P5n input pin INTn input pin 1 P5n output pin 139 8.5.4 Pin States Table 8-13 shows the port 5 pin states in each operating mode. Table 8-13 Port 5 Pin States Pins P57/INT7 to P50/INT0 Reset Sleep Subsleep Retains previous state Standby Watch Subactive Active Functional HighRetains impedance previous state HighRetains Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.5.5 MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n PUCR5n MOS input pull-up Note: * Don't care 0 Off 0 1 On 1 * Off (n = 7 to 0) 140 8.6 Port 6 8.6.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8-5. P67 P66 P65 Port 6 P64 P63 P62 P61 P60 Figure 8-5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8-14 shows the port 6 register configuration. Table 8-14 Port 6 Registers Name Port data register 6 Port control register 6 Abbrev. PDR6 PCR6 R/W R/W W Initial Value H'00 H'00 Address H'FFD9 H'FFE9 141 1. Bit Port data register 6 (PDR6) 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. Upon reset, PDR6 is initialized to H'00. 2. Port control register 6 (PCR6) Bit Initial value Read/Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register, which always reads all 1s. 142 8.6.3 Pin Functions Table 8-15 shows the port 6 pin functions. Table 8-15 Port 6 Pin Functions Pin P67 to P60 Pin Functions and Selection Method The pin function depends on bit PCR6n in PCR6 (n = 7 to 0) PCR6n Pin function 0 1 P6n input pin P6n output pin 8.6.4 Pin States Table 8-16 shows the port 6 pin states in each operating mode. Table 8-16 Port 6 Pin States Pin P67 toP60 Reset Sleep Subsleep Retains previous state Standby Watch Subactive Active Functional HighRetains impedance previous state HighRetains Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 143 8.7 Port 7 8.7.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8-6. P77 P76/TMOV P75/TMCIV Port 7 P74/TMRIV P73 P72 P71 P70 Figure 8-6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description Table 8-17 shows the port 7 register configuration. Table 8-17 Port 7 Registers Name Port data register 7 Port control register 7 Abbrev. PDR7 PCR7 R/W R/W W Initial Value H'00 H'00 Address H'FFDA H'FFEA 144 1. Bit Port data register 7 (PDR7) 7 P7 7 0 R/W 6 P7 6 0 R/W 5 P75 0 R/W 4 P7 4 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. 2. Bit Initial value Read/Write Port control register 7 (PCR7) 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register, which always reads as all 1s. 145 8.7.3 Pin Functions Table 8-18 shows the port 7 pin functions. Table 8-18 Port 7 Pin Functions Pin P77, P73 to P70 PCR7n Pin function P76/TMOV 0 Pin Functions and Selection Method The pin function depends on bit PCR7n in PCR7. (n = 7 or 3 to 0) 1 P7n input pin P7n output pin The pin function depends on bit PCR76 in PCR7 and bits OS3 to OS0 in TCSRV. OS3 to OS0 PCR76 Pin function 0 0000 1 Not 0000 * TMOV output pin P76 input pin P76 output pin P75/TMCIV The pin function depends on bit PCR75 in PCR7. PCR75 Pin function 0 1 P75 input pin P75 output pin TMCIV input pin P74/TMRIV The pin function depends on bit PCR74 in PCR7. PCR74 Pin function 0 1 P74 input pin P74 output pin TMRIV input pin Note: * Don't care 8.7.4 Pin States Table 8-19 shows the port 7 pin states in each operating mode. Table 8-19 Port 7 Pin States Pins P77 P76/TMOV P75/TMCIV P74/TMRIV P73 to P70 Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 146 8.8 Port 8 8.8.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8-7. P87 P86/FTID P85/FTIC Port 8 P84/FTIB P83//FTIA P82/FTOB P81/FTOA P80/FTCI Figure 8-7 Port 8 Pin Configuration 8.8.2 Register Configuration and Description Table 8-20 shows the port 8 register configuration. Table 8-20 Port 8 Registers Name Port data register 8 Port control register 8 Abbrev. PDR8 PCR8 R/W R/W W Initial Value H'00 H'00 Address H'FFDB H'FFEB 147 1. Port data register 8 (PDR8) Bit Initial value Read/Write 7 P8 7 0 R/W 6 P8 6 0 R/W 5 P85 0 R/W 4 P8 4 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P8 0 0 R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. 2. Port control register 8 (PCR8) Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register, which is always read as all 1s. 148 8.8.3 Pin Functions Table 8-24 shows the port 8 pin functions. Table 8-21 Port 8 Pin Functions Pin P87 Pin Functions and Selection Method The pin function depends on bit PCR87 in PCR8. PCR87 Pin function P86/FTID 0 1 P87 input pin P87 output pin The pin function depends on bit PCR86 in PCR8. PCR86 Pin function 0 1 P86 input pin P86 output pin FTID input pin P85/FTIC The pin function depends on bit PCR85 in PCR8. PCR85 Pin function 0 1 P85 input pin P85 output pin FTIC input pin P84/FTIB The pin function depends on bit PCR84 in PCR8. P84 Pin function 0 1 P84 input pin P84 output pin FTIB input pin P83/FTIA The pin function depends on bit PCR83 in PCR8. PCR83 Pin function 0 1 P83 input pin P83 output pin FTIA input pin P82/FTOB The pin function depends on bit PCR82 in PCR8 and bit OEB in TOCR. OEB PCR82 Pin function 0 0 1 1 * FTOB output pin P82 input pin P82 output pin Note: * Don't care 149 Table 8-21 Port 8 Pin Functions (cont) Pin P81/FTOA Pin Functions and Selection Method The pin function depends on bit PCR81 in PCR8 and bit OEA in TOCR. OEA PCR81 Pin function P80/FTCI 0 0 1 1 * FTOA output pin P81 input pin P81 output pin The pin function depends on bit PCR80 in PCR8. PCR80 Pin function 0 1 P80 input pin P80 output pin FTCI input pin Note: * Don't care 8.8.4 Pin States Table 8-22 shows the port 8 pin states in each operating mode. Table 8-22 Port 8 Pin States Pins P87 P86/FTID P85/FTIC P84/FTIB P83/FTIA P82/FTOB P81/FTOA P80/FTCI Reset Sleep Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Functional HighRetains impedance previous state Retains Functional previous state 150 8.9 Port 9 8.9.1 Overview Port 9 is a 5-bit I/O port, configured as shown in figure 8-8. P9 4 P9 3 Port 9 P9 2 P9 1 P9 0 Figure 8-8 Port 9 Pin Configuration 8.9.2 Register Configuration and Description Table 8-23 shows the port 9 register configuration. Table 8-23 Port 9 Registers Name Port data register 9 Port control register 9 Abbrev. PDR9 PCR9 R/W R/W W Initial Value H'C0 H'C0 Address H'FFDC H'FFEC 1. Port data register 9 (PDR9) Bit Initial value Read/Write 7 -- 1* -- 6 -- 1* -- 5 -- 0** -- 4 P94 0 R/W 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 P90 0 R/W Note: * Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified. ** Bit 5 is reserved; it is always read as 0 and cannot be modified. PDR9 is an 8-bit register that stores data for port 9 pins P94 to P90. If port 9 is read while PCR9 bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is read while PCR9 bits are cleared to 0, the pin states are read. Upon reset, PDR9 is initialized to H'C0. 151 2. Port control register 9 (PCR9) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 P94 0 W 3 P93 0 W 2 P92 0 W 1 P91 0 W 0 P90 0 W PCR9 controls whether each of the port 9 pins P94 to P90 functions as an input pin or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR9 is initialized to H'C0. PCR9 is a write-only register, which is always reads as all 1. 8.9.3 Pin Functions Table 8-24 shows the port 9 pin functions. Table 8-24 Port 9 Pin Functions Pin P9n Pin Functions and Selection Method The pin function depends on bit PCR9n in PCR9. (n = 4 to 0) PCR9n Pin function 0 P9n input pin 1 P9n output pin 8.9.4 Pin States Table 8-25 shows the port 9 pin states in each operating mode. Table 8-25 Port 9 Pin States Pins P94 to P90 Reset Highimpedance Sleep Retains previous state Subsleep Retains previous state Standby Highimpedance Watch Subactive Active Retains Functional Functional previous state 152 8.10 Port B 8.10.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8-9. PB7 /AN 7 PB6 /AN 6 PB5 /AN 5 Port B PB4 /AN 4 PB3 /AN 3 PB2 /AN 2 PB1 /AN 1 PB0 /AN 0 Figure 8-9 Port B Pin Configuration 8.10.2 Register Configuration and Description Table 8-26 shows the port B register configuration. Table 8-26 Port B Register Name Port data register B Abbrev. PDRB R/W R Address H'FFDD Port Data Register B (PDRB) Bit 7 PB 7 Read/Write R 6 PB6 R 5 PB5 R 4 PB 4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB 0 R Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 153 8.10.3 Pin Functions Table 8-27 shows the port B pin functions. Table 8-27 Port B Pin Functions Pin PBn/ANn Pin Functions and Selection Method Always as below. (n = 7 to 0) Pin function PBn input pin or ANn input pin 8.10.4 Pin States Table 8-28 shows the port B pin states in each operating mode. Table 8-28 Port B Pin States Pin PB7/AN7 to PB0/AN0 Reset Sleep Subsleep Highimpedance Standby Highimpedance Watch Highimpedance Subactive Highimpedance Active Highimpedance HighHighimpedance impedance 8.11 Usage Notes The following points should be noted when using I/O ports. (1) Handling of unused pins in input ports Unused pins in an input port should be connected to the power supply (VCC or VSS) so that the pins do not go to the floating (high-impedance) state. (2) Handling of unused pins in input/output ports Unused pins in an input/output port should be connected to the power supply (VCC or VSS), or else designated as output pins by setting the corresponding port control register bits by software immediately after reset release, so that the pins do not go to the floating (high-impedance) state. 154 Section 9 Timers 9.1 Overview The H8/3657 Series provides five timers: timers A, B1, V, X, and a watchdog timer. The functions of these timers are outlined in table 9-1. Table 9-1 Timer Functions Name Timer A Functions * 8-bit interval timer * Time base * Clock output Internal Clock o/8 to o/8192 (8 choices) oW/128 (choice of 4 overflow periods) o/4 to o/32 oW/4 to oW/32 (8 choices) o/4 to o/8192 (7 choices) -- TMOW Event Input Pin -- Waveform Output Pin -- Remarks Timer B1 * 8-bit reload timer * Interval timer * Event counter TMIB -- Timer V * 8-bit timer o/4 to o/128 * Event counter (6 choices) * Output control by dual compare match * Counter clearing option * Start of incrementing specifiable by external trigger input * 16-bit free-running timer * 2 output compare channels * 4 input capture channels * Counter clearing option * Event counter o/2 to o/32 (3 choices) TMCIV TMOV Timer X FTCI FTIA FTIB FTIC FTID FTOA FTOB Watchdog * Reset signal timer generated when 8-bit counter overflows o/8192 -- -- 155 9.2 Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. 1. Features Features of timer A are given below. * * Choice of eight internal clock sources (o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8). Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator). An interrupt is requested when the counter overflows. Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4. * * 156 2. Block diagram Figure 9-1 shows a block diagram of timer A. oW 1/4 oW/4 PSW TMA oW /128 TCA /128* /256* TMOW o/32 o/16 o/8 o/4 o o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8 PSS /64* /8* IRRTA Notation: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (oW/128) is used as the TCA input clock. Figure 9-1 Block Diagram of Timer A 3. Pin configuration Table 9-2 shows the timer A pin configuration. Table 9-2 Pin Configuration Name Clock output Abbrev. TMOW I/O Output Function Output of waveform generated by timer A output circuit 157 Internal data bus oW /32 oW /16 oW /8 oW /4 4. Register configuration Table 9-3 shows the register configuration of timer A. Table 9-3 Timer A Registers Name Timer mode register A Timer counter A Abbrev. TMA TCA R/W R/W R Initial Value H'10 H'00 Address H'FFB0 H'FFB1 9.2.2 Register Descriptions 1. Timer mode register A (TMA) Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. Bits 7 to 5: Clock output select (TMA7 to TMA5) Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. Bit 7 TMA7 0 Bit 6 TMA6 0 Bit 5 TMA5 0 1 1 0 1 1 0 0 1 1 0 1 Clock Output o/32 o/16 o/8 o/4 oW/32 oW/16 oW/8 oW/4 (initial value) 158 Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 0 Bit 2 TMA2 0 Bit 1 TMA1 0 Bit 0 TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, o/8192 PSS, o/4096 PSS, o/2048 PSS, o/512 PSS, o/256 PSS, o/128 PSS, o/32 PSS, o/8 PSW, 1 s PSW, 0.5 s PSW, 0.25 s PSW, 0.03125 s PSW and TCA are reset Clock time base (initial value) Function Interval timer 159 2. Timer counter A (TCA) Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation 1. Interval timer operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see 3.3, Interrupts. 160 2. Real-time clock time base operation When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. 3. Clock output Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, subactive mode, and subsleep mode. 9.2.4 Timer A Operation States Table 9-4 summarizes the timer A operation states. Table 9-4 Timer A Operation States Operation Mode TCA Interval Clock time base TMA Reset Active Reset Reset Reset Sleep Watch Subactive Halted Subsleep Halted Standby Halted Functions Functions Halted Functions Functions Functions Functions Functions Halted Functions Retained Retained Functions Retained Retained Note: When the real-time clock time base function is selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/o (s) in the count cycle. 161 9.3 Timer B1 9.3.1 Overview Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operation modes, interval and auto reload. 1. Features Features of timer B1 are given below. * Choice of seven internal clock sources (o/8192, o/2048, o/512, o/256, o/64, o/16, o/4) or an external clock (can be used to count external events). An interrupt is requested when the counter overflows. Block diagram * 2. Figure 9-2 shows a block diagram of timer B1. TMB1 o PSS TCB1 TMIB TLB1 Notation: TMB1: Timer mode register B1 TCB1: Timer counter B1 TLB1: Timer load register B1 IRRTB1: Timer B1 interrupt request flag PSS: Prescaler S Figure 9-2 Block Diagram of Timer B1 162 Internal data bus IRRTB1 3. Pin configuration Table 9-5 shows the timer B1 pin configuration. Table 9-5 Pin Configuration Name Timer B1 event input Abbrev. TMIB I/O Input Function Event input to TCB1 4. Register configuration Table 9-6 shows the register configuration of timer B1. Table 9-6 Timer B1 Registers Name Timer mode register B1 Timer counter B1 Timer load register B1 Abbrev. TMB1 TCB1 TLB1 R/W R/W R W Initial Value H'78 H'00 H'00 Address H'FFB2 H'FFB3 H'FFB3 9.3.2 Register Descriptions 1. Timer mode register B1 (TMB1) Bit Initial value Read/Write 7 TMB17 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 TMB12 0 R/W 1 TMB11 0 R/W 0 TMB10 0 R/W TMB1 is an 8-bit read/write register for selecting the auto-reload function and input clock. Upon reset, TMB1 is initialized to H'78. Bit 7: Auto-reload function select (TMB17) Bit 7 selects whether timer B1 is used as an auto-reload timer. Bit 7 TMB17 0 1 Description Interval timer function selected Auto-reload function selected (initial value) 163 Bits 6 to 3: Reserved bits Bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. Bits 2 to 0: Clock select (TMB12 to TMB10) Bits 2 to 0 select the clock input to TCB1. For external event counting, either the rising or falling edge can be selected. Bit 2 TMB12 0 0 0 0 1 1 1 1 Bit 1 TMB11 0 0 1 1 0 0 1 1 Bit 0 TMB10 0 1 0 1 0 1 0 1 Description Internal clock: o/8192 Internal clock: o/2048 Internal clock: o/512 Internal clock: o/256 Internal clock: o/64 Internal clock: o/16 Internal clock: o/4 External event (TMIB): rising or falling edge* (initial value) Note: * The edge of the external event signal is selected by bit INTEG6 in interrupt edge select register 2 (IEGR2). See 3.3.2, Interrupt Control Registers, for details. 2. Timer counter B1 (TCB1) Bit Initial value Read/Write 7 TCB17 0 R 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3 TCB13 0 R 2 TCB12 0 R 1 TCB11 0 R 0 TCB10 0 R TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in timer mode register B1 (TMB1). TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 bit in IRR1 is set to 1. TCB1 is allocated to the same address as TLB1. Upon reset, TCB1 is initialized to H'00. 164 3. Timer load register B1 (TLB1) Bit Initial value Read/Write 7 TLB17 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 TLB13 0 W 2 TLB12 0 W 1 TLB11 0 W 0 TLB10 0 W TLB1 is an 8-bit write-only register for setting the reload value of timer counter B1 (TCB1). When a reload value is set in TLB1, the same value is loaded into timer counter B1 (TCB1) as well, and TCB1 starts counting up from that value. When TCB1 overflows during operation in autoreload mode, the TLB1 value is loaded into TCB1. Accordingly, overflow periods can be set within the range of 1 to 256 input clocks. The same address is allocated to TLB1 as to TCB1. Upon reset, TLB1 is initialized to H'00. 9.3.3 Timer Operation 1. Interval timer operation When bit TMB17 in timer mode register B1 (TMB1) is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer B1 is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by bits TMB12 to TMB10 of TMB1. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow, setting bit IRRTB1 to 1 in interrupt request register 1 (IRR1). If IENTB1 = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCB1 returns to H'00 and starts counting up again. During interval timer operation (TMB17 = 0), when a value is set in timer load register B1 (TLB1), the same value is set in TCB1. Note: * For details on interrupts, see 3.3, Interrupts. 165 2. Auto-reload timer operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value. The overflow period can be set within a range from 1 to 256 input clocks, depending on the TLB1 value. The clock sources and interrupts in auto-reload mode are the same as in interval mode. In auto-reload mode (TMB17 = 1), when a new value is set in TLB1, the TLB1 value is also set in TCB1. 3. Event counter operation Timer B1 can operate as an event counter, counting rising or falling edges of an external event signal input at pin TMIB. External event counting is selected by setting bits TMB12 to TMB10 in timer mode register B1 to all 1s (111). When timer B1 is used to count external event input, bit INTEN6 in IENR3 should be cleared to 0 to disable INT6 interrupt requests. 9.3.4 Timer B1 Operation States Table 9-7 summarizes the timer B1 operation states. Table 9-7 Timer B1 Operation States Operation Mode TCB1 Interval Reset Reset Active Functions Functions Functions Sleep Functions Functions Retained Watch Halted Halted Retained Subactive Halted Halted Subsleep Halted Halted Standby Halted Halted Auto reload Reset TMB1 Reset Retained Retained Retained 166 9.4 Timer V 9.4.1 Overview Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. 1. Features Features of timer V are given below. * Choice of six internal clock sources (o/128, o/64, o/32, o/16, o/8, o/4) or an external clock (can be used as an external event counter). Counter can be cleared by compare match A or B, or by an external reset signal. If the trigger function is selected, the counter can be halted when cleared. Timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, PWM output, and other applications. Three interrupt sources: two compare match, one overflow Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or both edges of the TRGV input can be selected. * * * * 167 2. Block diagram Figure 9-3 shows a block diagram of timer V. TCRV1 TCORB TRGV Trigger control Comparator TMCIV Clock select TCNTV Internal data bus Interrupt request control CMIA CMIB OVI Comparator o PSS TCORA TMRIV Clear control TCRVO TMOV Output control TCSRV Notation: TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B Overflow interrupt Figure 9-3 Block Diagram of Timer V 168 3. Pin configuration Table 9-8 shows the timer V pin configuration. Table 9-8 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input Abbrev. TMOV TMCIV TMRIV TRGV I/O Output Input Input Input Function Timer V waveform output Clock input to TCNTV External input to reset TCNTV Trigger input to initiate counting 4. Register configuration Table 9-9 shows the register configuration of timer V. Table 9-9 Timer V Registers Name Timer control register V0 Timer control/status register V Time constant register A Time constant register B Timer counter V Timer control register V1 Abbrev. TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 R/W R/W R/(W)* R/W R/W R/W R/W Initial Value H'00 H'10 H'FF H'FF H'00 H'E2 Address H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD Note: * Bits 7 to 5 can only be written with 0, for flag clearing. 169 9.4.2 Register Descriptions 1. Bit Initial value Read/Write Timer counter V (TCNTV) 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input. The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and written by the CPU at any time. TCNTV can be cleared by an external reset signal, or by compare match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0. When TCNTV overflows from H'FF to H'00, OVF is set to 1 in TCSRV. TCNTV is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 2. Time constant registers A and B (TCORA, TCORB) Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W n = A or B TCORn7 TCORn6 TCORn5 TCORn4 TCORn3 TCORn2 TCORn1 TCORn0 TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times, except during the T3 state of a TCORA write cycle. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Timer output from the TMOV pin can be controlled by a signal resulting from compare match, according to the settings of bits OS3 to OS0 in TCSRV. TCORA is initialized to H'FF upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. TCORB is similar to TCORA. 170 3. Bit Timer control register V0 (TCRV0) 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write TCRV0 is an 8-bit read/write register that selects the TCNTV input clock, controls the clearing of TCNTV, and enables interrupts. TCRV0 is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7: Compare match interrupt enable B (CMIEB) Bit 7 enables or disables the interrupt request (CMIB) generated from CMFB when CMFB is set to 1 in TCSRV. Bit 7 CMIEB 0 1 Description Interrupt request (CMIB) from CMFB disabled Interrupt request (CMIB) from CMFB enabled (initial value) Bit 6: Compare match interrupt enable A (CMIEA) Bit 6 enables or disables the interrupt request (CMIA) generated from CMFA when CMFA is set to 1 in TCSRV. Bit 6 CMIEA 0 1 Description Interrupt request (CMIA) from CMFA disabled Interrupt request (CMIA) from CMFA enabled (initial value) Bit 5: Timer overflow interrupt enable B (OVIE) Bit 5 enables or disables the interrupt request (OVI) generated from OVF when OVF is set to 1 in TCSRV. Bit 5 OVIE 0 1 Description Interrupt request (OVI) from OVF disabled Interrupt request (OVI) from OVF enabled (initial value) 171 Bits 4 and 3: Counter clear 1 and 0 (CCLR1, CCLR0) Bits 4 and 3 specify whether or not to clear TCNTV, and select compare match A or B or an external reset input. When clearing is specified, if TRGE is set to 1 in TCRV1, then when TCNTV is cleared it is also halted. Counting resumes when a trigger edge is input at the TRGV pin. If TRGE is cleared to 0, after TCNTV is cleared it continues counting up. Bit 4 CCLR1 0 0 1 1 Bit 3 CCLR0 0 1 0 1 Description Clearing is disabled Cleared by compare match A Cleared by compare match B Cleared by rising edge of external reset input (initial value) Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0) Bits 2 to 0 and bit ICKS0 in TCRV1 select the clock input to TCNTV. Six internal clock sources divided from the system clock (o) can be selected. The counter increments on the falling edge. If the external clock is selected, there is a further selection of incrementing on the rising edge, falling edge, or both edges. If TRGE is cleared to 0, after TCNTV is cleared it continues counting up. TCRV0 Bit 2 CKS2 0 0 0 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 0 1 1 1 1 0 0 1 1 Bit 0 CKS0 0 1 1 0 0 1 1 0 1 0 1 TCRV1 Bit 0 ICKS0 -- 0 1 0 1 0 1 -- -- -- -- Description Clock input disabled Internal clock: o/4, falling edge Internal clock: o/8, falling edge Internal clock: o/16, falling edge Internal clock: o/32, falling edge Internal clock: o/64, falling edge Internal clock: o/128, falling edge Clock input disabled External clock: rising edge External clock: falling edge External clock: rising and falling edges (initial value) 172 4. Timer control/status register V (TCSRV) Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Bits 7 to 5 can be only written with 0, for flag clearing. TCSRV is an 8-bit register that sets compare match flags and the timer overflow flag, and controls compare match output. TCSRV is initialized to H'10 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7: Compare match flag B (CMFB) Bit 7 is a status flag indicating that TCNTV has matched TCORB. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 CMFB 0 1 Description Clearing conditions: After reading CMFB = 1, cleared by writing 0 to CMFB Setting conditions: Set when the TCNTV value matches the TCORB value (initial value) Bit 6: Compare match flag A (CMFA) Bit 6 is a status flag indicating that TCNTV has matched TCORA. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 CMFA 0 1 Description Clearing conditions: After reading CMFA = 1, cleared by writing 0 to CMFA Setting conditions: Set when the TCNTV value matches the TCORA value (initial value) 173 Bit 5: Timer overflow flag (OVF) Bit 5 is a status flag indicating that TCNTV has overflowed from H'FF to H'00. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 5 OVF 0 1 Description Clearing conditions: After reading OVF = 1, cleared by writing 0 to OVF Setting conditions: Set when TCNTV overflows from H'FF to H'00 (initial value) Bit 4: Reserved bit Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0: Output select 3 to 0 (OS3 to OS0) Bits 3 to 0 select the way in which the output level at the TMOV pin changes in response to compare match between TCNTV and TCORA or TCORB. OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two levels can be controlled independently. If two compare matches occur simultaneously, any conflict between the settings is resolved according to the following priority order: toggle output > 1 output > 0 output. When OS3 to OS0 are all cleared to 0, timer output is disabled. After a reset, the timer output is 0 until the first compare match. Bit 3 OS3 0 0 1 1 Bit 1 OS1 0 0 1 1 Bit 2 OS2 0 1 0 1 Bit 0 OS0 0 1 0 1 Description No change at compare match B 0 output at compare match B 1 output at compare match B Output toggles at compare match B (initial value) Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A (initial value) 174 5. Timer control register V1 (TCRV1) Bit Initial value Read/Write 7 -- 1 -- 6 ---- 1 -- 5 -- 1 -- 4 TVEG1 0 R/W 3 TVEG0 0 R/W 2 TRGE 0 R/W 1 -- 1 -- 0 ICKS0 0 R/W TCRV1 is an 8-bit read/write register that selects the valid edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. TCRV1 is initialized to H'E2 upon reset and in watch mode, subsleep mode, and subactive mode. Bits 7 to 5: Reserved bits Bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bits 4 and 3: TRGV input edge select (TVEG1, TVEG0) Bits 4 and 3 select the TRGV input edge. Bit 4 TVEG1 0 0 1 1 Bit 3 TVEG0 0 1 0 1 Description TRGV trigger input is disabled Rising edge is selected Falling edge is selected Rising and falling edges are both selected (initial value) Bit 2: TRGV input enable (TRGE) Bit 2 enables or disables TCNTV counting to be triggered by input at the TRGV pin, and enables or disables TCNTV counting to be halted when TCNTV is cleared by compare match. TCNTV stops counting when TRGE is set to 1, then starts counting when the edge selected by bits TVEG1 and TVEG0 is input at the TRGV pin. Bit 2 TRGE 0 1 Description TCNTV counting is not triggered by input at the TRGV pin, and does not stop when TCNTV is cleared by compare match (initial value) TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV is cleared by compare match 175 Bit 1: Reserved bit Bit 1 is reserved; it is always read as 1, and cannot be modified. Bit 0: Internal clock select 0 (ICKS0) Bit 0 and bits CKS2 to CKS0 in TCRV0 select the TCNTV clock source. For details see 9.8.2 (3), Timer control register V0. 9.4.3 Timer Operation 1. Timer V operation A reset initializes TCNTV to H'00, TCORA and TCORB to H'FF, TCRV0 to H'00, TCSRV to H'10, and TCRV1 to H'E2. Timer V can be clocked by one of six internal clocks output from prescaler S, or an external clock, as selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. The valid edge or edges of the external clock can also be selected by CKS2 to CKS0. When the clock source is selected, TCNTV starts counting the selected clock input. The TCNTV contents are always compared with TCORA and TCORB. When a match occurs, the CMFA or CMFB bit is set to 1 in TCSRV. If CMIEA or CMIEB is set to 1 in TCRV0, a CPU interrupt is requested. At the same time, the output level selected by bits OS3 to OS0 in TCSRV is output from the TMOV pin. When TCNT overflows from H'FF to H'00, if OVIE is 1 in TCRV0, a CPU interrupt is requested. If bits CCLR1 and CCLR0 in TCRV0 are set to 01 (clear by compare match A) or 10 (clear by compare match B), TCNTV is cleared by the corresponding compare match. If these bits are set to 11, TCNTV is cleared by input of a rising edge at the TMRIV pin. If bit TRGE is set to 1 in TCRV1, when TCNTV is cleared by the event selected by bits CCLR1 and CCLR0, it is also halted. TCNTV starts counting when the signal edge selected by bits TVEG1 and TVEG0 in TCRV1 is input at the TRGV pin. 176 2. TCNTV increment timing TCNTV is incremented by an input (internal or external) clock. * Internal clock One of six clocks (o/128, o/64, o/32, o/16, o/8, o/4) divided from the system clock (o) can be selected by bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1. Figure 9-4 shows the timing. o Internal clock FRC input TCNTV input TCNTV N-1 N N-1 Figure 9-4 Increment Timing with Internal Clock * External clock Incrementation on the rising edge, falling edge, or both edges of the external clock can be selected by bits CKS2 to CKS0 in TCRV0. The external clock pulse width should be at least 1.5 system clocks (o) when a single edge is counted, and at least 2.5 system clocks when both edges are counted. Shorter pulses will not be counted correctly. Figure 9-5 shows the timing when both the rising and falling edges of the external clock are selected. 177 o TMCIV (external clock input pin) TCNTV input clock TCNTV N-1 N N-1 Figure 9-5 Increment Timing with External Clock 3. Overflow flag set timing The overflow flag (OVF) is set to 1 when TCNTV overflows from H'FF to H'00. Figure 9-6 shows the timing. o TCNTV H'FF H'00 Overflow signal Figure 9-6 OVF Set Timing 178 4. Compare match flag set timing Compare match flag A or B (CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB. The internal compare-match signal is generated in the last state in which the values match (when TCNTV changes from the matching value to a new value). Accordingly, when TCNTV matches TCORA or TCORB, the compare match signal is not generated until the next clock input to TCNTV. Figure 9-7 shows the timing. o TCNTV N N+1 TCORA or TCORB Compare match signal N CMFA or CMFB Figure 9-7 CMFA and CMFB Set Timing 5. TMOV output timing The TMOV output responds to compare match A or B by remaining unchanged, changing to 0, changing to 1, or toggling, as selected by bits OS3 to OS0 in TCSRV. Figure 9-8 shows the timing when the output is toggled by compare match A. o Compare match A signal Timer V output pin Figure 9-8 TMOV Output Timing 179 6. TCNTV clear timing by compare match TCNTV can be cleared by compare match A or B, as selected by bits CCLR1 and CCLR0 in TCRV0. Figure 9-9 shows the timing. o Compare match A signal TCNTV N H'00 Figure 9-9 Clear Timing by Compare Match 7. TCNTV clear timing by TMRIV TCNTV can be cleared by a rising edge at the TMRIV pin, as selected by bits CCLR1 and CCLR0 in TCRV0. A TMRIV input pulse width of at least 1.5 system clocks is necessary. Figure 9-10 shows the timing. o Compare match A signal Timer V output pin TCNTV N-1 N H'00 Figure 9-10 Clear Timing by TMRIV Input 180 9.4.4 Timer V Operation Modes Table 9-10 summarizes the timer V operation states. Table 9-10 Timer V Operation States Operation Mode TCNTV TCRV0, TCRV1 TCORA, TCORB TCSRV Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Functions Functions Functions Watch Reset Reset Reset Reset Subactive Reset Reset Reset Reset Subsleep Reset Reset Reset Reset Standby Reset Reset Reset Reset 9.4.5 Interrupt Sources Timer V has three interrupt sources: CMIA, CMIB, and OVI. Table 9-11 lists the interrupt sources and their vector address. Each interrupt source can be enabled or disabled by an interrupt enable bit in TCRV0. Although all three interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. Table 9-11 Timer V Interrupt Sources Interrupt CMIA CMIB OVI Description Generated from CMFA Generated from CMFB Generated from OVF Vector Address H'0022 181 9.4.6 Application Examples 1. Pulse output with arbitrary duty cycle Figure 9-11 shows an example of output of pulses with an arbitrary duty cycle. To set up this output: * * * Clear bit CCLR1 to 0 and set bit CCLR0 to 1 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. With these settings, a waveform is output without further software intervention, with a period determined by TCORA and a pulse width determined by TCORB. TCNTV H'FF TCORA TCORB H'00 Counter cleared TMOV Figure 9-11 Pulse Output Example 2. Single-shot output with arbitrary pulse width and delay from TRGV input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 9-12. To set up this output: * * * * Set bit CCLR1 to 1 and clear bit CCLR0 to 0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. Set bits OS3 to OS0 to 0110 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. Set bits TVEG1 and TVEG0 to 10 in TCRV1 and set TRGE to 1 to select the falling edge of the TRGV input. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 182 After these settings, a pulse waveform will be output without further software intervention, with a delay determined by TCORA from the TRGV input, and a pulse width determined by (TCORB - TCORA). H'FF TCORB TCORA H'00 TRGV TCNTV Counter cleared TMOV Compare match A Compare match B clears and halts TCNTV Compare match A Compare match B clears and halts TCNTV Figure 9-12 Pulse Output Synchronized to TRGV Input 183 9.4.7 Application Notes The following types of contention can occur in timer V operation. 1. Contention between TCNTV write and counter clear If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, clearing takes precedence and the write to the counter is not carried out. Figure 9-13 shows the timing. TCNTV write cycle by CPU T1 T2 T3 o Address TCNTV address Internal write signal Counter clear signal TCNTV N H'00 Figure 9-13 Contention between TCNTV Write and Clear 184 2. Contention between TCNTV write and increment If a TCNTV increment clock signal is generated in the T3 state of a TCNTV write cycle, the write takes precedence and the counter is not incremented. Figure 9-14 shows the timing. TCNTV write cycle by CPU T1 T2 T3 o Address TCNTV address Internal write signal TCNTV clock TCNTV N M TCNTV write data Figure 9-14 Contention between TCNTV Write and Increment 185 3. Contention between TCOR write and compare match If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure 9-15 shows the timing. TCORA write cycle by CPU T1 T2 T3 o Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 9-15 Contention between TCORA Write and Compare Match 186 4. Contention between compare match A and B If compare match A and B occur simultaneously, any conflict between the output selections for compare match A and compare match B is resolved by following the priority order in table 9-12. Table 9-12 Timer Output Priority Order Output Setting Toggle output 1 output 0 output No change Low Priority High 5. Internal clock switching and counter operation Depending on the timing, TCNTV may be incremented by a switch between different internal clock sources. Table 9-13 shows the relation between internal clock switchover timing (by writing to bits CKS1 and CKS0) and TCNTV operation. When TCNTV is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (o). For this reason, in a case like No. 3 in table 9-13 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a switch between internal and external clocks. 187 Table 9-13 Internal Clock Switching and TCNTV Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level*1 No. 1 TCNTV Operation Clock before switching Clock after switching Count clock TCNTV N Write to CKS1 and CKS0 N+1 2 Goes from low to high*2 Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Notes: 1. Including a transition from the low level to the stopped state, or from the stopped state to the low level. 2. Including a transition from the stopped state to the high level. 188 Table 9-13 Internal Clock Switching and TCNTV Operation (cont) Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to low level*1 No. 3 TCNTV Operation Clock before switching Clock after switching *2 Count clock TCNTV N N+1 Write to CKS1 and CKS0 N+2 4 Goes from high to high Clock before switching Clock after switching Count clock TCNTV N N +1 N +2 Write to CKS1 and CKS0 Notes: 1. Including a transition from the high level to the stopped state. 2. The switchover is seen as a falling edge, and TCNTV is incremented. 189 9.5 Timer X 9.5.1 Overview Timer X is based on a 16-bit free-running counter (FRC). It can output two independent waveforms, or measure input pulse widths and external clock periods. 1. Features Features of timer X are given below. * Choice of three internal clock sources (o/2, o/8, o/32) or an external clock (can be used as an external event counter). Two independent output compare waveforms. Four independent input capture channels, with selection of rising or falling edge and buffering option. Counter can be cleared by compare match A. Seven independent interrupt sources: two compare match, four input capture, one overflow * * * * 190 2. Block diagram Figure 9-16 shows a block diagram of timer X. ICRA FTIA FTIB FTIC FTID Input capture control ICRC ICRB ICRD TCRX OCRB Comparator FRC FTCI Comparator OCRA TOCR Internal data bus Interrupt request Timer interrupt enable register Timer control/status register X Free-running counter Output compare register A Output compare register B Timer control register X Timer output compare control register Input capture register A Input capture register B Input capture register C Input capture register D Prescaler S o FTOA FTOB PSS TCSRX TIER Notation: TIER: TCSRX: FRC: OCRA: OCRB: TCRX: TOCR: ICRA: ICRB: ICRC: ICRD: PSS: Figure 9-16 Block Diagram of Timer X 191 3. Pin configuration Table 9-14 shows the timer X pin configuration. Table 9-14 Pin Configuration Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D Abbrev. FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function Clock input to FRC Output pin for output compare A Output pin for output compare B Input pin for input capture A Input pin for input capture B Input pin for input capture C Input pin for input capture D 192 4. Register configuration Table 9-15 shows the register configuration of timer X. Table 9-15 Timer X Registers Name Timer interrupt enable register Timer control/status register X Free-running counter H Free-running counter L Output compare register AH Output compare register AL Output compare register BH Output compare register BL Timer control register X Timer output compare control register Input capture register AH Input capture register AL Input capture register BH Input capture register BL Input capture register CH Input capture register CL Input capture register DH Input capture register DL Abbrev. TIER TCSRX FRCH FRCL OCRAH OCRAL OCRBH OCRBL TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL R/W R/W R/(W)*1 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Initial Value H'01 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'E0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 Address H'F770 H'F771 H'F772 H'F773 H'F774*2 H'F775*2 H'F774*2 H'F775*2 H'F776 H'F777 H'F778 H'F779 H'F77A H'F77B H'F77C H'F77D H'F77E H'F77F Notes: 1. Bits 7 to 1 can only be written with 0 for flag clearing. Bit 0 is a read/write bit. 2. OCRA and OCRB share the same address. They are selected by the OCRS bit in TOCR. 193 9.5.2 Register Descriptions 1. Free-running counter (FRC) Free-running counter H (FRCH) Free-running counter L (FRCL) FRC Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input. The clock source is selected by bits CKS1 and CKS0 in TCRX. FRC can be cleared by compare match A, depending on the setting of CCLRA in TCSRX. When FRC overflows from H'FFFF to H'0000, OVF is set to 1 in TCSRX. If OVIE = 1 in TIER, a CPU interrupt is requested. FRC can be written and read by the CPU. Since FRC has 16 bits, data is transferred between the CPU and FRC via a temporary register (TEMP). For details see 9.5.3, CPU Interface. FRC is initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 2. Output compare registers A and B (OCRA, OCRB) Output compare registers AH and BH (OCRAH, OCRBH) Output compare registers AL and BL (OCRAL, OCRBL) OCRA, OCRB Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAH, OCRBH OCRAL, OCRBL There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in TCSRX. If 194 OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested. When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the output from the FTOA or FTOB pin is 0 until the first compare match occurs. OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is transferred between them and the CPU via a temporary register (TEMP). For details see 9.5.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 3. Input capture registers A to D (ICRA to ICRD) Input capture registers AH to DH (ICRAH to ICRDH) Input capture registers AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL There are four 16-bit read only input capture registers, ICRA to ICRD. When the falling edge of an input capture signal is input, the FRC value is transferred to the corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in TIER, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits IEDGA to IEDGD in TCRX. ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by bits BUFEA and BUFEB in TCRX. Figure 9-17 shows the interconnections when ICRC operates as a buffer register of ICRA (when BUFEA = 1). In buffered input capture operations, both the rising and falling edges of the external input signal can be selected simultaneously, by setting IEDGA IEDGC. If IEDGA = IEDGC, then only one edge is selected (either the rising edge or falling edge). See table 9-16. Note: The FRC value is transferred to the input capture register (ICR) regardless of the value of the input capture flag (ICF). 195 IEOGA BUFEA IEDGC FTIA Edge detector and internal capture signal generator ICRC ICRA FRC Figure 9-17 Buffer Operation (Example) Table 9-16 Input Edge Selection during Buffer Operation IEDGA 0 0 1 1 IEDGC 0 1 0 1 Rising edge of input capture A input signal is captured Input Edge Selection Falling edge of input capture A input signal is captured (initial value) Rising and falling edge of input capture A input signal are both captured ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is transferred from them to the CPU via a temporary register (TEMP). For details see 9.5.3, CPU Interface. To assure input capture, the pulse width of the input capture input signal must be at least 1.5 system clocks (o) when a single edge is selected, or at least 2.5 system clocks (o) when both edges are selected. ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 196 4. Bit Timer interrupt enable register (TIER) 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 -- Initial value Read/Write TIER is an 8-bit read/write register that enables or disables interrupt requests. TIER is initialized to H'01 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7: Input capture interrupt A enable (ICIAE) Bit 7 enables or disables the ICIA interrupt requested when ICFA is set to 1 in TCSRX. Bit 7 ICIAE 0 1 Description Interrupt request by ICFA (ICIA) is disabled Interrupt request by ICFA (ICIA) is enabled (initial value) Bit 6: Input capture interrupt B enable (ICIBE) Bit 6 enables or disables the ICIB interrupt requested when ICFB is set to 1 in TCSRX. Bit 6 ICIBE 0 1 Description Interrupt request by ICFB (ICIB) is disabled Interrupt request by ICFB (ICIB) is enabled (initial value) Bit 5: Input capture interrupt C enable (ICICE) Bit 5 enables or disables the ICIC interrupt requested when ICFC is set to 1 in TCSRX. Bit 5 ICICE 0 1 Description Interrupt request by ICFC (ICIC) is disabled Interrupt request by ICFC (ICIC) is enabled (initial value) 197 Bit 4: Input capture interrupt D enable (ICIDE) Bit 4 enables or disables the ICID interrupt requested when ICFD is set to 1 in TCSRX. Bit 4 ICIDE 0 1 Description Interrupt request by ICFD (ICID) is disabled Interrupt request by ICFD (ICID) is enabled (initial value) Bit 3: Output compare interrupt A enable (OCIAE) Bit 3 enables or disables the OCIA interrupt requested when OCFA is set to 1 in TCSRX. Bit 3 OCIAE 0 1 Description Interrupt request by OCFA (OCIA) is disabled Interrupt request by OCFA (OCIA) is enabled (initial value) Bit 2: Output compare interrupt B enable (OCIBE) Bit 2 enables or disables the OCIB interrupt requested when OCFB is set to 1 in TCSRX. Bit 2 OCIBE 0 1 Description Interrupt request by OCFB (OCIB) is disabled Interrupt request by OCFB (OCIB) is enabled (initial value) Bit 1: Timer overflow interrupt enable (OVIE) Bit 1 enables or disables the FOVI interrupt requested when OVF is set to 1 in TCSRX. Bit 1 OVIE 0 1 Description Interrupt request by OVF (FOVI) is disabled Interrupt request by OVF (FOVI) is enabled (initial value) Bit 0: Reserved bit Bit 0 is reserved; it is always read as 1, and cannot be modified. 198 5. Bit Timer control/status register X (TCSRX) 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 CCLRA 0 R/W Initial value Read/Write Note: * Bits 7 to 1 can only be written with 0 for flag clearing. TCSRX is an 8-bit register that selects clearing of the counter and controls interrupt request signals. TCSRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Other timing is described in section 9-6-3, Timer Operation. Bit 7: Input capture flag A (ICFA) Bit 7 is a status flag that indicates that the FRC value has been transferred to ICRA by an input capture signal. If BUFEA is set to 1 in TCRX, ICFA indicates that the FRC value has been transferred to ICRA by an input capture signal and that the ICRA value before this update has been transferred to ICRC. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7 ICFA 0 1 Description Clearing conditions: After reading ICFA = 1, cleared by writing 0 to ICFA (initial value) Setting conditions: Set when the FRC value is transferred to ICRA by an input capture signal Bit 6: Input capture flag B (ICFB) Bit 6 is a status flag that indicates that the FRC value has been transferred to ICRB by an input capture signal. If BUFEB is set to 1 in TCRX, ICFB indicates that the FRC value has been transferred to ICRB by an input capture signal and that the ICRB value before this update has been transferred to ICRD. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6 ICFB 0 1 Description Clearing conditions: After reading ICFB = 1, cleared by writing 0 to ICFB (initial value) Setting conditions: Set when the FRC value is transferred to ICRB by an input capture signal 199 Bit 5: Input capture flag C (ICFC) Bit 5 is a status flag that indicates that the FRC value has been transferred to ICRC by an input capture signal. If BUFEA is set to 1 in TCRX, ICFC is set by the input capture signal even though the FRC value is not transferred to ICRC. In buffered operation, ICFC can accordingly be used as an external interrupt, by setting the ICICE bit to 1. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 5 ICFC 0 1 Description Clearing conditions: After reading ICFC = 1, cleared by writing 0 to ICFC Setting conditions: Set by input capture signal (initial value) Bit 4: Input capture flag D (ICFD) Bit 4 is a status flag that indicates that the FRC value has been transferred to ICRD by an input capture signal. If BUFEB is set to 1 in TCRX, ICFD is set by the input capture signal even though the FRC value is not transferred to ICRD. In buffered operation, ICFD can accordingly be used as an external interrupt, by setting the ICIDE bit to 1. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 4 ICFD 0 1 Description Clearing conditions: After reading ICFD = 1, cleared by writing 0 to ICFD Setting conditions: Set by input capture signal (initial value) Bit 3: Output compare flag A (OCFA) Bit 3 is a status flag that indicates that the FRC value has matched OCRA. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3 OCFA 0 1 Description Clearing conditions: After reading OCFA = 1, cleared by writing 0 to OCFA Setting conditions: Set when FRC matches OCRA (initial value) 200 Bit 2: Output compare flag B (OCFB) Bit 2 is a status flag that indicates that the FRC value has matched OCRB. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 OCFB 0 1 Description Clearing conditions: After reading OCFB = 1, cleared by writing 0 to OCFB Setting conditions: Set when FRC matches OCRB (initial value) Bit 1: Timer overflow flag (OVF) Bit 1 is a status flag that indicates that FRC has overflowed from H'FFFF to H'0000. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 1 OVF 0 1 Description Clearing conditions: After reading OVF = 1, cleared by writing 0 to OVF Setting conditions: Set when the FRC value overflows from H'FFFF to H'0000 (initial value) Bit 0: Counter clear A (CCLRA) Bit 0 selects whether or not to clear FRC by compare match A (when FRC matches OCRA). Bit 0 CCLRA 0 1 Description FRC is not cleared by compare match A FRC is cleared by compare match A (initial value) 201 6. Bit Timer control register X (TCRX) 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value Read/Write TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals, enables buffering, and selects the FRC clock source. TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bit 7: Input edge select A (IEDGA) Bit 7 selects the rising or falling edge of the input capture A input signal (FTIA). Bit 7 IEDGA 0 1 Description Falling edge of input A is captured Rising edge of input A is captured (initial value) Bit 6: Input edge select B (IEDGB) Bit 6 selects the rising or falling edge of the input capture B input signal (FTIB). Bit 6 IEDGB 0 1 Description Falling edge of input B is captured Rising edge of input B is captured (initial value) Bit 5: Input edge select C (IEDGC) Bit 5 selects the rising or falling edge of the input capture C input signal (FTIC). Bit 5 IEDGC 0 1 Description Falling edge of input C is captured Rising edge of input C is captured (initial value) 202 Bit 4: Input edge select D (IEDGD) Bit 4 selects the rising or falling edge of the input capture D input signal (FTID). Bit 4 IEDGD 0 1 Description Falling edge of input D is captured Rising edge of input D is captured (initial value) Bit 3: Buffer enable A (BUFEA) Bit 3 selects whether or not to use ICRC as a buffer register for ICRA. Bit 3 BUFEA 0 1 Description ICRC is not used as a buffer register for ICRA ICRC is used as a buffer register for ICRA (initial value) Bit 2: Buffer enable B (BUFEB) Bit 2 selects whether or not to use ICRD as a buffer register for ICRB. Bit 2 BUFEB 0 1 Description ICRD is not used as a buffer register for ICRB ICRD is used as a buffer register for ICRB (initial value) Bits 1 and 0: Clock select (CKS1, CKS0) Bits 1 and 0 select one of three internal clock sources or an external clock for input to FRC. The external clock is counted on the rising edge. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description Internal clock: o/2 Internal clock: o/8 Internal clock: o/32 External clock: rising edge (initial value) 203 7. Bit Timer output compare control register (TOCR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W Initial value Read/Write TOCR is an 8-bit read/write register that selects the output compare output levels, enables output compare output, and controls access to OCRA and OCRB. TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. Bits 7 to 5: Reserved bits Bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. Bit 4: Output compare register select (OCRS) OCRA and OCRB share the same address. OCRS selects which register is accessed when this address is written or read. It does not affect the operation of OCRA and OCRB. Bit 4 OCRS 0 1 Description OCRA is selected OCRB is selected (initial value) Bit 3: Output enable A (OEA) Bit 3 enables or disables the timer output controlled by output compare A. Bit 3 OEA 0 1 Description Output compare A output is disabled Output compare A output is enabled (initial value) 204 Bit 2: Output enable B (OEB) Bit 2 enables or disables the timer output controlled by output compare B. Bit 2 OEB 0 1 Description Output compare B output is disabled Output compare B output is enabled (initial value) Bit 1: Output level A (OLVLA) Bit 1 selects the output level that is output at pin FTOA by compare match A (when FRC matches OCRA). Bit 1 OLVLA 0 1 Description Low level High level (initial value) Bit 0: Output level B (OLVLB) Bit 0 selects the output level that is output at pin FTOB by compare match B (when FRC matches OCRB). Bit 0 OLVLB 0 1 Description Low level High level (initial value) 9.5.3 CPU Interface FRC, OCRA, OCRB, and ICRA to ICRD are 16-bit registers, but the CPU is connected to the onchip peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers should always be accessed 16 bits at a time. If two consecutive byte-size MOV instructions are used, the upper byte must be accessed first and the lower byte second. Data will not be transferred correctly if only the upper byte or only the lower byte is accessed. 205 1. Write access Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. Figure 9-18 shows an example of the writing of H'AA55 to FRC. Write to upper byte CPU (H'AA) Bus interface Module data bus TEMP (H'AA) FRCH ( ) FRCL ( ) Write to lower byte Module data bus CPU (H'55) Bus interface TEMP (H'AA) FRCH (H'AA) FRCL (H'55) Figure 9-18 Write Access to FRC (CPU FRC) 206 2. Read access In access to FRC and ICRA to ICRD, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRA or OCRB, when the upper byte is read the upper-byte data is transferred directly to the CPU, and when the lower byte is read the lower-byte data is transferred directly to the CPU. Figure 9-19 shows an example of the reading of FRC when FRC contains H'AAFF. Read upper byte CPU (H'AA) Bus interface Module data bus TEMP (H'FF) FRCH (H'AA) FRCL (H'FF) Read lower byte Module data bus CPU (H'FF) Bus interface TEMP (H'FF) FRCH ( AB ) FRCL ( 00 ) Note: * H'AB00 if counter has been updated once. Figure 9-19 Read Access to FRC (FRC CPU) 207 9.5.4 Timer Operation 1. * Timer operation Output compare operation Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources or an external clock for input to FRC. The FRC contents are compared constantly with OCRA and OCRB. When a match occurs, the output at pin FTOA or FTOB goes to the level selected by OLVLA or OLVLB in TOCR. Following a reset, the output at both FTOA and FTOB is 0 until the first compare match. If CCLRA is set to 1 in TCSRX, compare match A clears FRC to H'0000. * Input capture operation Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources or an external clock for input to FRC. When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA to FTID, the FRC value is transferred to ICRA to ICRD, and ICFA to ICFD are set in TCSRX. If bits ICIAE to ICIDE are set to 1 in TIER, a CPU interrupt is requested. If bits BUFEA and BUFEB are set to 1 in TCRX, ICRC and ICRD operate as buffer registers for ICRA or ICRB. When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA and FTIB, the FRC value is transferred to ICRA or ICRB, and the previous value in ICRA or ICRB is transferred to ICRC or ICRD. Simultaneously, ICFA or ICFB is set in TCSRX. If bit ICIAE or ICIBE is set to 1 in TIER, a CPU interrupt is requested. 208 2. FRC count timing FRC is incremented by clock input. Bits CKS1 and CKS0 in TCRX can select one of three internal clock sources (o/2, o/8, o/32) or an external clock. * Internal clock Bits CKS1 and CKS0 in TCRX select one of three internal clock sources (o/2, o/8, o/32) created by dividing the system clock (o). Figure 9-20 shows the increment timing. o Internal clock FRC input clock FRC N-1 N N+1 Figure 9-20 Increment Timing with Internal Clock 209 * External clock External clock input is selected when bits CKS1 and CKS0 are both set to 1 in TCRX. FRC increments on the rising edge of the external clock. An external pulse width of at least 1.5 system clocks (o) is necessary. Shorter pulses will not be counted correctly. Figure 9-21 shows the timing. o FTCI (external clock input pin) FRC input clock FRC N N-1 Figure 9-21 Increment Timing with External Clock 210 3. Output compare timing When a compare match occurs, the output level selected by the OLVL bit in TOCR is output at pin FTOA or FTOB. Figure 9-22 shows the output timing for output compare A. o FRC N N+1 N N+1 OCRA N Compare match A signal Clear* OLVLA FTOA (output compare A output pin) Note: * By execution of a software instruction. Figure 9-22 Output Compare A Output Timing 211 4. FRC clear timing FRC can be cleared by compare match A. Figure 9-23 shows the timing. o Compare match A signal FRC N H'0000 Figure 9-23 Clear Timing by Compare Match A 5. * Input capture timing Input capture timing The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX. Figure 9-24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1). o Input capture pin Internal input capture signal Figure 9-24 Input Capture Signal Timing (Normal Case) If the input at the input capture pin occurs while the upper byte of the corresponding input capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by one system clock (o). Figure 9-25 shows the timing. 212 ICRA-ICRD upper byte read cycle T1 o T2 T3 Input capture pin Internal input capture signal Figure 9-25 Input Capture Signal Timing (during ICRA-ICRD Read) * Buffered input capture timing Input capture can be buffered by using ICRC or ICRD as a buffer for ICRA or ICRB. Figure 9-26 shows the timing when ICRA is buffered by ICRC (BUFEA = 1) and both the rising and falling edges are selected (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1). o FTIA Internal input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 9-26 Buffered Input Capture Timing (Normal Case) 213 When ICRC or ICRD is used as a buffer register, the input capture flag is still set by the selected edge of the input capture input signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs at the input capture pin, ICFC will be set, and if the ICIEC bit is set to 1, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered operation, if the upper byte of one of the two registers that receives a data transfer (ICRA and ICRC, or ICRB and ICRD) is being read when an internal input capture signal would normally occur, the internal input capture signal will be delayed by one system clock (o). Figure 9-27 shows the case when BUFEA = 1. ICRA or ICRC upper byte read cycle by CPU T1 o T2 T3 FTIA Internal input capture signal Figure 9-27 Buffered Input Capture Signal Timing (during ICRA or ICRC Read) 214 6. Input capture flag (ICFA to ICFD) set timing Figure 9-28 shows the timing when an input capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input capture register (ICRA to ICRD). o Internal input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 9-28 ICFA to ICFD Set Timing 7. Output compare flag (OCFA or OCFB) set timing OCFA and OCFB are set to 1 by internal compare match signals that are output when FRC matches OCRA or OCRB. The compare match signal is generated in the last state during which the values match (when FRC is updated from the matching value to a new value). When FRC matches OCRA or OCRB, the compare match signal is not generated until the next counter clock. Figure 9-29 shows the OCFA and OCFB set timing. 215 o FRC N N+1 OCRA, OCRB N Internal compare match signal OCFA, OCFB Figure 9-29 OCFA and OCFB Set Timing 8. Overflow flag (OVF) set timing OVF is set to 1 when FRC overflows from H'FFFF to H'0000. Figure 9-30 shows the timing. o FRC H'FFFF H'0000 Overflow signal OVF Figure 9-30 OVF Set Timing 216 9.5.5 Timer X Operation Modes Figure 9-17 shows the timer X operation modes. Table 9-17 Timer X Operation Modes Operation Mode FRC OCRA, OCRB ICRA to ICRD TIER TCRX TOCR TCSRX Reset Reset Reset Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Functions Functions Functions Sleep Functions Functions Functions Functions Functions Functions Functions Watch Reset Reset Reset Reset Reset Reset Reset Subactive Reset Reset Reset Reset Reset Reset Reset Subsleep Reset Reset Reset Reset Reset Reset Reset Standby Reset Reset Reset Reset Reset Reset Reset 9.5.6 Interrupt Sources Timer X has three types of interrupts and seven interrupt sources: ICIA to ICID, OCIA, OCIB, and FOVI. Table 9-18 lists the sources of interrupt requests. Each interrupt source can be enabled or disabled by an interrupt enable bit in TIER. Although all seven interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. Table 9-18 Timer X Interrupt Sources Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Description Interrupt requested by ICFA Interrupt requested by ICFB Interrupt requested by ICFC Interrupt requested by ICFD Interrupt requested by OCFA Interrupt requested by OCFB Interrupt requested by OVF Vector Address H'0020 217 9.5.7 Timer X Application Example Figure 9-31 shows an example of the output of pulse signals with a 50% duty cycle and arbitrary phase offset. To set up this output: * * Set bit CCLRA to 1 in TCSRX. Have software invert the OLVLA and OLVLB bits at each corresponding compare match. FRC H'FFFF OCRA OCRB H'0000 FTOA Counter cleared FTOB Figure 9-31 Pulse Output Example 218 9.5.8 Application Notes The following types of contention can occur in timer X operation. 1. Contention between FRC write and counter clear If an FRC clear signal is generated in the T3 state of a write cycle to the lower byte of FRC, clearing takes precedence and the write to the counter is not carried out. Figure 9-32 shows the timing. FRC lower byte write cycle T1 T2 T3 o Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 9-32 Contention between FRC Write and Clear 219 2. Contention between FRC write and increment If an FRC increment clock signal is generated in the T3 state of a write cycle to the lower byte of FRC, the write takes precedence and the counter is not incremented. Figure 9-33 shows the timing. FRC lower byte write cycle T1 T2 T3 o Address FRC address Internal write signal FRC input clock FRC N M FRC write data Figure 9-33 Contention between FRC Write and Increment 220 3. Contention between OCR write and compare match If a compare match is generated in the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is inhibited. Figure 9-34 shows the timing. OCR lower byte write cycle T1 T2 T3 o Address OCR address Internal write signal FRC N N+1 OCR N M Write data Internal compare match signal Inhibited Figure 9-34 Contention between OCR Write and Compare Match 221 4. Internal clock switching and counter operation Depending on the timing, FRC may be incremented by a switch between different internal clock sources. Table 9-19 shows the relation between internal clock switchover timing (by writing to bits CKS1 and CKS0) and FRC operation. When FRC is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (o). For this reason, in a case like No. 3 in table 9-19 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing FRC to increment. FRC can also be incremented by a switch between internal and external clocks. Table 9-19 Internal Clock Switching and FRC Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level No. 1 FRC Operation Clock before switching Clock after switching Count clock FRC N Write to CKS1 and CKS0 N+1 2 Goes from low to high Clock before switching Clock after switching Count clock FRC N N+1 N+2 Write to CKS1 and CKS0 222 Table 9-19 Internal Clock Switching and FRC Operation (cont) Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to low level No. 3 FRC Operation Clock before switching Clock after switching * Count clock FRC N N+1 Write to CKS1 and CKS0 N+2 4 Goes from high to high Clock before switching Clock after switching Count clock FRC N N+1 N+2 Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and FRC is incremented. 223 9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. Features Features of the watchdog timer are given below. * * Incremented by internal clock source (o/8192). A reset signal is generated when the counter overflows. The overflow period can be set from from 1 to 256 times 8192/o (from approximately 2 ms to 500 ms when o = 4.19 MHz). Block diagram 2. Figure 9-35 shows a block diagram of the watchdog timer. TCSRW Internal data bus Reset signal o PSS o/8192 TCW Notation: TCSRW: Timer control/status register W TCW: Timer counter W PSS: Prescaler S Figure 9-35 Block Diagram of Watchdog Timer 224 3. Register configuration Table 9-20 shows the register configuration of the watchdog timer. Table 9-20 Watchdog Timer Registers Name Timer control/status register W Timer counter W Abbrev. TCSRW TCW R/W R/W R/W Initial Value H'AA H'00 Address H'FFBE H'FFBF 9.6.2 Register Descriptions 1. Timer control/status register W (TCSRW) Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/W * 5 B4WI 1 R 4 TCSRWE 0 R/W * 3 B2WI 1 R 2 WDON 0 R/W* 1 B0WI 1 R 0 WRST 0 R/W * Note: * Write is permitted only under certain conditions, which are given in the descriptions of the individual bits. TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself, controls watchdog timer operations, and indicates operating status. Bit 7: Bit 6 write inhibit (B6WI) Bit 7 controls the writing of data to bit 6 in TCSRW. Bit 7 B6WI 0 1 Description Bit 6 is write-enabled Bit 6 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. 225 Bit 6: Timer counter W write enable (TCWE) Bit 6 controls the writing of data to TCW. Bit 6 TCWE 0 1 Description Data cannot be written to TCW Data can be written to TCW (initial value) Bit 5: Bit 4 write inhibit (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI 0 1 Description Bit 4 is write-enabled Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 4: Timer control/status register W write enable (TCSRWE) Bit 4 controls the writing of data to TCSRW bits 2 and 0. Bit 4 TCSRWE 0 1 Description Data cannot be written to bits 2 and 0 Data can be written to bits 2 and 0 (initial value) Bit 3: Bit 2 write inhibit (B2WI) Bit 3 controls the writing of data to bit 2 in TCSRW. Bit 3 B2WI 0 1 Description Bit 2 is write-enabled Bit 2 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. 226 Bit 2: Watchdog timer on (WDON) Bit 2 enables watchdog timer operation. Bit 2 WDON 0 Description Watchdog timer operation is disabled (initial value) Clearing conditions: Reset, or when TCSRWE = 1 and 0 is written in both B2WI and WDON Watchdog timer operation is enabled Setting conditions: When TCSRWE = 1 and 0 is written in B2WI and 1 is written in WDON 1 Counting starts when this bit is set to 1, and stops when this bit is cleared to 0. Bit 1: Bit 0 write inhibit (B0WI) Bit 1 controls the writing of data to bit 0 in TCSRW. Bit 1 B0WI 0 1 Description Bit 0 is write-enabled Bit 0 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 0: Watchdog timer reset (WRST) Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the RES pin, or when software writes 0. Bit 0 WRST 0 Description Clearing conditions: * Reset by RES pin * When TCSRWE = 1, and 0 is written in both B0WI and WRST Setting conditions: When TCW overflows and an internal reset signal is generated (initial value) 1 227 2. Bit Timer counter W (TCW) 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 TCW3 0 R/W 2 TCW2 0 R/W 1 TCW1 0 R/W 0 TCW0 0 R/W Initial value Read/Write TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input clock is o/8192. The TCW value can always be written or read by the CPU. When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to 1 in TCSRW. Upon reset, TCW is initialized to H'00. 9.6.3 Timer Operation The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (o/8192). When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow and generates an internal reset signal. The internal reset signal is output for 512 clock cycles of the oOSC clock. It is possible to write to TCW, causing TCW to count up from the written value. The overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in TCW. 228 Figure 9-36 shows an example of watchdog timer operations. Example: o = 4 MHz and the desired overflow period is 30 ms. 4 x 106 x 30 x 10-3 = 14.6 8192 The value set in TCW should therefore be 256 - 15 = 241 (H'F1). H'FF H'F1 TCW count value TCW overflow H'00 Start H'F1 written in TCW Internal reset signal 512 oOSC clock cycles H'F1 written in TCW Reset Figure 9-36 Typical Watchdog Timer Operations (Example) 9.6.4 Watchdog Timer Operation States Table 9-21 summarizes the watchdog timer operation states. Table 9-21 Watchdog Timer Operation States Operation Mode TCW TCSRW Reset Reset Reset Active Functions Functions Sleep Functions Functions Watch Halted Retained Subactive Halted Retained Subsleep Halted Retained Standby Halted Retained 229 Section 10 Serial Communication Interface 10.1 Overview The H8/3657 Series is provided with a two-channel serial communication interface (SCI). Table 10-1 summarizes the functions and features of the two SCI channels. Table 10-1 Serial Communication Interface Functions Channel SCI1 Functions Synchronous serial transfer * Choice of 8-bit or 16-bit data length * Continuous clock output SCI3 Synchronous serial transfer * 8-bit data length * Send, receive, or simultaneous send/receive Asynchronous serial transfer * Multiprocessor communication * Choice of 7-bit or 8-bit data length * Choice of 1 or 2 stop bits * Parity addition Features * Choice of 8 internal clocks (o/1024 to o/2) or external clock * Open drain output possible * Interrupt requested at completion of transfer * On-chip baud rate generator * Receive error detection * Break detection * Interrupt requested at completion of transfer or error 10.2 SCI1 10.2.1 Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. SSB (Synchronized Serial Bus) communication is also provided, enabling multiple ICs to be controlled. 1. * * Features Choice of 8-bit or 16-bit data length Choice of eight internal clock sources (o/1024, o/256, o/64, o/32, o/16, o/8, o/4, o/2) or an external clock Interrupt requested at completion of transfer Choice of HOLD mode or LATCH mode in SSB mode * * 231 2. Block diagram Figure 10-1 shows a block diagram of SCI1. o PSS SCK1 SCR1 Transfer bit counter SI1 SDRU SDRL SO1 IRRS1 Notation: SCR1: Serial control register 1 SCSR1: Serial control/status register 1 SDRU: Serial data register U SDRL: Serial data register L IRRS1: SCI1 interrupt request flag PSS: Prescaler S Figure 10-1 SCI1 Block Diagram 232 Internal data bus Transmit/receive control circuit SCSR1 3. Pin configuration Table 10-2 shows the SCI1 pin configuration. Table 10-2 Pin Configuration Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbrev. SCK1 SI1 SO1 I/O I/O Input Output Function SCI1 clock input or output SCI1 receive data input SCI1 transmit data output 4. Register configuration Table 10-3 shows the SCI1 register configuration. Table 10-3 SCI1 Registers Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Abbrev. SCR1 SCSR1 SDRU SDRL R/W R/W R/W R/W R/W Initial Value H'00 H'9C Not fixed Not fixed Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 10.2.2 Register Descriptions 1. Serial control register 1 (SCR1) Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the transfer. 233 Bits 7 and 6: Operation mode select 1, 0 (SNC1, SNC0) Bits 7 and 6 select the operation mode. Bit 7 SNC1 0 0 1 1 Bit 6 SNC0 0 1 0 1 Description 8-bit synchronous transfer mode 16-bit synchronous transfer mode Continuous clock output mode*1 Reserved*2 (initial value) Notes: 1. Pins SI1 and SO1 should be used as general input or output ports. 2. Don't set bits SNC1 and SNC0 to 11. Bits 5: TAIL MARK control (MRKON) Bit 5 controls TAIL MARK output after an 8- or 16-bit data transfer. Bit 5 MRKON 0 1 Description TAIL MARK is not output (synchronous mode) TAIL MARK is output (SSB mode) (initial value) Bits 4: LATCH TAIL select (LTCH) Bit 4 selects whether LATCH TAIL or HOLD TAIL is output as TAIL MARK when bit MRKON is set to 1 (SSB mode). Bit 4 LTCH 0 1 Description HOLD TAIL is output LATCH TAIL is output (initial value) Bit 3: Clock source select (CKS3) Bit 3 selects the clock source and sets pin SCK1 as an input or output pin. Bit 3 CKS3 0 1 Description Clock source is prescaler S, and pin SCK1 is output pin Clock source is external clock, and pin SCK1 is input pin* (initial value) Note: * Input an external clock equivalent to a frequency lower than o/4. 234 Bits 2 to 0: Clock select (CKS2 to CKS 0) When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Serial Clock Cycle Prescaler Division o/1024 (initial value) o/256 o/64 o/32 o/16 o/8 o/4 o/2 o = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s -- o = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s 235 2. Serial control/status register 1 (SCSR1) Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 MTRF 0 R 0 STF 0 R/W Note: * Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'9C. Bit 7: Reserved bit Bit 7 is reserved; it is always read as 1, and cannot be modified. Bit 6: Extended data bit (SOL) Bit 6 sets the SO1 output level. When read, SOL returns the output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. The setting is also invalid in SSB mode. To control the level of the SO1 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this register while transmission is in progress, because that may cause a malfunction. Bit 6 SOL 0 Description Read: SO1 pin output level is low Write: SO1 pin output level changes to low 1 Read: SO1 pin output level is high Write: SO1 pin output level changes to high (initial value) 236 Bit 5: Overrun error flag (ORER) When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. Bit 5 ORER 0 1 Description Clearing conditions: After reading ORER = 1, cleared by writing 0 to ORER (initial value) Setting conditions: Set if a clock pulse is input after transfer is complete, when an external clock is used Bits 4 to 2: Reserved bits Bits 4 to 2 are reserved. They are always read as 0, and cannot be modified. Bit 1: TAIL MARK transmit flag (MTRF) When bit MRKON is set to 1, bit 1 indicates that TAIL MARK is being sent. Bit 1 is a read-only bit and cannot be modified. Bit 1 MTRF 0 1 Description Idle state, or 8- or 16-bit data is being transferred TAIL MARK is being sent (initial value) Bit 0: Start flag (STF) Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared to 0 upon completion of the transfer. It can therefore be used as a busy flag. Bit 0 STF 0 Description Read: Indicates that transfer is stopped Write: Invalid 1 Read: Indicates transfer in progress Write: Starts a transfer operation (initial value) 237 3. Serial data register U (SDRU) Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 SDRU3 R/W 2 SDRU2 R/W 1 0 SDRU1 SDRU0 R/W R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is not fixed. 4. Serial data register L (SDRL) Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 SDRL3 R/W 2 SDRL2 R/W 1 SDRL1 R/W 0 SDRL0 R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU. SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is not fixed. 238 10.2.3 Operation in Synchronous Mode Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external serial clock. Overrun errors can be detected when an external clock is used. 1. Clock The serial clock can be selected from a choice of eight internal clocks and an external clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (o/1024 to o/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When an external clock is used, pin SCK1 is the clock input pin. 2. Data transfer format Figure 10-2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next rising edge. Receive data is latched at the rising edge of the serial clock. SCK 1 SO1 /SI 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10-2 Transfer Format 3. * Data transfer operations Transmitting A transmit operation is carried out as follows. 1. Set bits SO1 and SCK1 to 1 in PMR3 to select the SO1 and SCK1 pin functions. If necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO1. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 2. 3. 239 4. 5. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1. After data transmission is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. * Receiving A receive operation is carried out as follows. 1. 2. Set bits SI1 and SCK1 to 1 in PMR3 to select the SI1 and SCK1 pin functions. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI1. After data reception is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 6. After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1. 3. 4. 5. 240 * Simultaneous transmit/receive A simultaneous transmit/receive operation is carried out as follows. 1. Set bits SO1, SI1, and SCK1 to 1 in PMR3 to select the SO1, SI1, and SCK1 pin functions. If necessary, set bit POF1 in PMR7 for NMOS open-drain output at pin SO1. Clear bit SNC1 in SCR1 to 0, set bit SNC0 to 0 or 1, and clear bit MRKON to 0, designating 8or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 when bit MRKON in SCR1 is cleared to 0 initializes the internal state of SCI1. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO1. Receive data is input at pin SI1. After data transmission and reception are complete, bit IRRS1 in IRR2 is set to 1. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK1. After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. 2. 3. 5. 6. 241 10.2.4 Operation in SSB Mode SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables multiple ICs to be connected as shown in figure 10-3. In SSB mode, TAIL MARK is sent after an 8- or 16-bit data transfer. HOLD TAIL or LATCH TAIL can be selected as TAIL MARK. H8/3657 SCK 1 Series LSI SO1 SCL SDA SDA SDA IC-A IC-B IC-C Figure 10-3 Example of SSB Connection 1. Clock The transfer clock can be selected from eight internal clocks or an external clock, but since the H8/3657 Series uses clock output, an external clock should not be selected. The transfer rate can be selected by bits CKS2 to CKS0 in SCR1. Since this is also the TAIL MARK transfer rate, the setting should be made to give a transfer clock cycle of at least 2 s. 242 SDA SCL SCL SCL 2. Data transfer format Figure 10-4 shows the SCI1 transfer format. Data is sent starting from the least significant bit, in LSB-first format. TAIL MARK is sent after an 8- or 16-bit data transfer. SCK1 SO 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 14 Bit 15 TAIL MARK 1 frame Figure 10-4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1) 3. TAIL MARK TAIL MARK can be either HOLD TAIL or LATCH TAIL. The output waveforms of HOLD TAIL and LATCH TAIL are shown in figure 10-5. Time t in the figure is determined by the transfer clock cycle set in bits CKS2 to CKS0 in SCR1. < HOLD TAIL > SCK1 t SO 1 t t 2t t t t SO 1 SCK1 t t t < LATCH TAIL > 2t t t Bit 14 Bit 15 Bit 0 Bit 14 Bit 15 Figure 10-5 HOLD TAIL and LATCH TAIL Waveforms 4. Transmitting A transmit operation is carried out as follows. 1. 2. Set bit SOL in SCSR1 to 1. Set bits SO1 and SCK1 to 1 in PMR3 to select the S01 and SCK1 pin functions. Set bit POF1 in PMR7 to 1 for NMOS open-drain output at pin SO1. 243 3. Clear bit SNC1 in SCR1 to 0 and set bit SNC0 to 0 or 1, designating 8-bit mode or 16-bit mode. Set bit MRKON in SCR1 to 1, selecting SSB mode. Write transmit data in SDRL and SDRU as follows, and select TAIL MARK with bit LTCH in SCR1. 8-bit mode: SDRL 16-bit mode: Upper byte in SDRU, lower byte in SDRL 4. 5. 6. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin S01. After 8- or 16-bit data transmission is complete, bit STF in SCSR1 is cleared to 0 and bit IRRS1 in interrupt request register 2 (IRRS1) is set to 1. The selected TAIL MARK is output after the data transmission. During TAIL MARK output, bit MTRF in SCSR1 is set to 1. Data can be sent continuously by repeating steps 4 to 6. Check that SCI1 is in the idle state before rewriting bit MRKON in SCR1. 10.2.5 Interrupts SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2 (IENR2). For further details, see 3.3, Interrupts. 244 10.3 SCI3 10.3.1 Overview Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors. 1. Features Features of SCI3 are listed below. * Choice of asynchronous or synchronous mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously, with synchronization provided character by character. In this mode, serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A multiprocessor communication function is also provided, enabling serial data communication among processors. There is a choice of 12 data transfer formats. Data length Stop bit length Parity Multiprocessor bit Receive error detection Break detection 7 or 8 bits 1 or 2 bits Even, odd, or none "1" or "0" Parity, overrun, and framing errors Break detected by reading the RXD pin level directly when a framing error occurs - Synchronous mode Serial data communication is synchronized with a clock. In his mode, serial data can be exchanged with another LSI that has a synchronous communication function. Data length Receive error detection 8 bits Overrun errors 245 * Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. * * * On-chip baud rate generator, allowing any desired bit rate to be selected Choice of an internal or external clock as the transmit/receive clock source Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error, framing error, and parity error 246 2. Block diagram Figure 10-6 shows a block diagram of SCI3. SCK 2 External clock Internal clock (o/64, o/16, o/4, o) Baud rate generator BRC Clock BRR Transmit/receive control circuit SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) Notation: RSR: RDR: TSR: TDR: SMR: SCR3: SSR: BRR: BRC: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Figure 10-6 SCI3 Block Diagram 247 Internal data bus SMR 3. Pin configuration Table 10-4 shows the SCI3 pin configuration. Table 10-4 Pin Configuration Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbrev. SCK3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output 4. Register configuration Table 10-5 shows the SCI3 register configuration. Table 10-5 Registers Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial data register Receive data register Transmit shift register Receive shift register Bit rate counter Abbrev. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC R/W R/W R/W R/W R/W R/W R Protected Protected Protected Initial Value H'00 H'FF H'00 H'FF H'84 H'00 -- -- -- Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD -- -- -- 10.3.2 Register Descriptions 1. Receive shift register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU. 248 2. Receive data register (RDR) Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R RDR is an 8-bit register that stores received serial data. When reception of one byte of data is finished, the received data is transferred from RSR to RDR, and the receive operation is completed. RSR is then enabled for reception. RSR and RDR are double-buffered, allowing consecutive receive operations. RDR is a read-only register, and cannot be written by the CPU. RDR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. 3. Transmit shift register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register (SSR)). TSR cannot be read or written directly by the CPU. 249 4. Transmit data register (TDR) Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. 5. Serial mode register (SMR) Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7: Communication mode (COM) Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode. Bit 7 COM 0 1 Description Asynchronous mode Synchronous mode (initial value) 250 Bit 6: Character length (CHR) Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous mode the data length is always 8 bits, irrespective of the bit 6 setting. Bit 6 CHR 0 1 Note: Description 8-bit data 7-bit data* * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. (initial value) Bit 5: Parity enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 PE 0 1 Note: Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (initial value) * When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit data before it is sent, and the received parity bit is checked against the parity designated by bit PM. Bit 4: Parity mode (PM) Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity bit addition and checking is disabled. Bit 4 PM 0 1 Notes: Description Even parity*1 Odd parity*2 (initial value) 1. When even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. 2. When odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. 251 Bit 3: Stop bit length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit*1 2 stop bits*2 (initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character. In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next transmit character. Bit 2: Multiprocessor mode (MP) Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is disabled, the parity settings in the PE and PM bits are invalid. The MP bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit should be set to 0. For details on the multiprocessor communication function, see 10.3.6, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor communication function disabled Multiprocessor communication function enabled (initial value) Bits 1 and 0: Clock select (CKS1, CKS0) Bits 1 and 0 choose o/64, o/16, o/4, or o as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate register (BRR). Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (initial value) 252 6. Serial control register 3 (SCR3) Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock output, interrupt request enabling or disabling, and the transmit/receive clock source. SCR3 can be read or written by the CPU at any time. SCR3 is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7: Transmit interrupt enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0. Bit 7 TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6: Receive interrupt enable (RIE) Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun, framing, and parity. RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing bit RIE to 0. Bit 6 RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled (initial value) 253 Bit 5: Transmit enable (TE) Bit 5 selects enabling or disabling of the start of transmit operation. Bit 5 TE 0 1 Description Transmit operation disabled*1 (TXD pin is transmit data pin) Transmit operation enabled*2 (TXD pin is transmit data pin) (initial value) Notes: 1. Bit TDRE in SSR is fixed at 1. Transmission operation is disabled, but the TXD pin functions as the transmit data pin. To use the TXD pin as an I/O pin, clear bit TXD in PMR7 to 0. 2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and serial data transmission is started. Be sure to carry out serial mode register (SMR) settings to decide the transmission format before setting bit TE to 1. Bit 4: Receive enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 RE 0 1 Description Receive operation disabled*1 (RXD pin is I/O port) Receive operation enabled*2 (RXD pin is receive data pin) (initial value) Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. 2. In this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. Be sure to carry out serial mode register (SMR) settings to decide the reception format before setting bit RE to 1. 254 Bit 3: Multiprocessor interrupt enable (MPIE) Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupt request disabled (normal receive operation) Clearing conditions: When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled* * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests (when bits TIE and RIE in serial control register 3 (SCR3) are set to 1) and setting of the RDRF, FER, and OER flags are enabled. (initial value) 1 Note: Bit 2: Transmit end interrupt enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE 0 1 Note: Description Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled* * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by clearing bit TEIE to 0. (initial value) 255 Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0) Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3 pin. These bits determine whether the SCK3 pin functions as an I/O port, a clock output pin, or a clock input pin. The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0 should be cleared to 0. After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR). For details on clock source selection, see table 10-10 in 10.3.3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Communication Mode Asynchronous Synchronous 0 1 Asynchronous Synchronous 1 0 Asynchronous Synchronous 1 1 Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved Clock input*3 Serial clock input SCK3 Pin Function I/O port*1 Serial clock output*1 Clock output*2 Notes: 1. Initial value 2. A clock with the same frequency as the bit rate is output. 3. Input a clock with a frequency 16 times the bit rate. 256 7. Serial status register (SSR) Bit Initial value Read/Write 7 TDRE 1 R/(W) * 6 RDRF 0 R/(W)* 5 OER 0 R/(W) * 4 FER 0 R/(W)* 3 PER 0 R/(W) * 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits. SSR can be read or written by the CPU at any time, but 1 cannot be written to bits TDRE, RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read. Bits TEND and MPBR are read-only bits, and cannot be modified. SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7: Transmit data register empty (TDRE) Bit 7 indicates that transmit data has been transferred from TDR to TSR. Bit 7 TDRE 0 Description Transmit data written in TDR has not been transferred to TSR Clearing conditions: * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR Setting conditions: * When bit TE in SCR3 is cleared to 0 * When data is transferred from TDR to TSR 1 (initial value) 257 Bit 6: Receive data register full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF 0 Description There is no receive data in RDR Clearing conditions: * After reading RDRF = 1, cleared by writing 0 to RDRF * When RDR data is read by an instruction (initial value) 1 There is receive data in PDR Setting conditions: When reception ends normally and receive data is transferred from RSR to RDR If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0, RDR and bit RDRF are not affected and retain their previous state. Note that if data reception is completed while bit RDRF is still set to 1, an overrun error (OER) will result and the receive data will be lost. Note: Bit 5: Overrun error (OER) Bit 5 indicates that an overrun error has occurred during reception. Bit 5 OER 0 Description Reception in progress or completed*1 Clearing conditions: After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception*2 Setting conditions: When reception is completed with RDRF set to 1 (initial value) 1 Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous state. 2. RDR retains the receive data it held before the overrun error occurred, and data received after the error is lost. Reception cannot be continued with bit OER set to 1, and in synchronous mode, transmission cannot be continued either. 258 Bit 4: Framing error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 FER 0 Description Reception in progress or completed*1 Clearing conditions: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception*2 Setting conditions: When the stop bit at the end of the receive data is checked for a value of 1 at the end of reception, and the stop bit is 0*2 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous state. 2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. When a framing error occurs the receive data is transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. (initial value) 1 Notes: Bit 3: Parity error (PER) Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode. Bit 3 PER 0 Description Reception in progress or completed*1 Clearing conditions: After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception*2 Setting conditions: When the number of 1 bits in the receive data plus parity bit does not match the parity designated by bit PM in the serial mode register (SMR) 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous state. 2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous mode, neither transmission nor reception is possible when bit FER is set to 1. (initial value) 1 Notes: 259 Bit 2: Transmit end (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND 0 Description Transmission in progress Clearing conditions: * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmission ended (initial value) Setting conditions: * When bit TE in SCR3 is cleared to 0 * When bit TDRE is set to 1 when the last bit of a transmit character is sent 1 Bit 1: Multiprocessor bit receive (MPBR) Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in asynchronous mode. Bit 1 is a read-only bit and cannot be modified. Bit 1 MPBR 0 1 Note: Description Data in which the multiprocessor bit is 0 has been received* Data in which the multiprocessor bit is 1 has been received * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not affected and retains its previous state. (initial value) Bit 0: Multiprocessor bit transfer (MPBT) Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when synchronous mode is selected, when the multiprocessor communication function is disabled, and when not transmitting. Bit 0 MPBT 0 1 Description A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted (initial value) 260 8. Bit rate register (BRR) Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. Table 10-6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) OSC (MHz) 2 R Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 -- -- -- 0 -- N 70 207 103 51 25 12 -- -- -- 0 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- -- 0 -- n 1 0 0 0 0 0 0 0 0 -- 0 2.4576 N 86 255 127 63 31 15 7 3 1 -- 0 Error (%) +0.31 0 0 0 0 0 0 0 0 -- 0 n 1 1 0 0 0 0 0 -- -- 0 -- 4 N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 -- -- -- 4.194304 N Error (%) 148 -0.04 108 +0.21 217 +0.21 108 +0.21 54 -0.70 26 +1.14 13 -2.48 6 -2.48 -- -- -- -- -- -- 261 Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) OSC (MHz) 4.9152 R Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 0 0 0 0 0 0 0 -- 6 N 212 155 77 155 77 38 19 9 4 2 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- n 2 1 1 0 0 0 0 0 0 -- 0 7.3728 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 -- 0 -- 8 N Error (%) 70 +0.03 207 +0.16 103 +0.16 207 +0.16 103 +0.16 51 +0.16 25 +0.16 12 +0.16 -- 3 -- -- 0 -- Table 10-6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) OSC (MHz) 9.8304 R Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 10 N 88 64 129 64 129 64 32 15 7 4 3 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 262 Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation: N= OSC x 106 -- 1 (64 x 22n x B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 N 255) OSC: Value of oOSC (MHz) n: Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 10-7.) Table 10-7 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 3. The error in table 10-6 is the value obtained from the following equation, rounded to two decimal places. Error (%) = B (rate obtained from n, N, OSC) -- R(bit rate in left-hand column in table 10-6.) x 100 R (bit rate in left-hand column in table 10-6.) 263 Table 10-8 shows the maximum bit rate for each frequency. The values shown are for active (highspeed) mode. Table 10-8 Maximum Bit Rate for Each Frequency (Asynchronous Mode) Maximum Bit Rate (bit/s) 31250 38400 62500 65536 76800 93750 115200 125000 153600 156250 Setting n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 OSC (MHz) 2 2.4576 4 4.194304 4.9152 6 7.3728 8 9.8304 10 264 Table 10-9 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10-9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) OSC (MHz) B Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M Blank: Cannot be set. -- : A setting can be made, but an error will result. * : Continuous transmission/reception is not possible. 2 n -- 1 1 0 0 0 0 0 0 -- 0 N -- 249 124 249 99 49 24 9 4 -- 0* n -- 2 1 1 0 0 0 0 0 0 0 0 4 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 10 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- 265 Notes: The value set in BRR is given by the following equation: N= OSC (8 x 22n x B) x 106 -- 1 where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 N 255) OSC: Value of oOSC (MHz) n: Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 10-10.) Table 10-10 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 266 10.3.3 Operation SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10-11. The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3, as shown in table 10-12. 1. * * Synchronous mode Choice of 7- or 8-bit data length Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.) Framing error (FER), parity error (PER), overrun error (OER), and break detection during reception Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock with the same frequency as the bit rate can be output. When external clock is selected: A clock with a frequency 16 times the bit rate must be input. (The on-chip baud rate generator is not used.) 2. * * * Synchronous mode Data transfer format: Fixed 8-bit data length Overrun error detection during reception Choice of internal or external clock as the clock source When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial clock is output. When external clock is selected: The on-chip baud rate generator is not used, and SCI3 operates on the input serial clock. * * 267 Table 10-11 SMR Settings and Corresponding Data Transfer Formats SMR bit 7 bit 6 bit 2 bit 5 bit 3 COM CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * * 1 * * 1 * 0 * 0 1 0 1 * Synchronous mode 8-bit data No No Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Yes No Yes 7-bit data No Asynchronous mode Data Length 8-bit data Data Transfer Format Multiprocessor Parity Stop Bit Bit Bit Length No No 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits No Table 10-12 SMR and SCR3 Settings and Clock Source Selection SMR SCR3 Transmit/Receive Clock Clock Source Internal SCK3 Pin Function I/O port (SCK3 pin not used) Outputs clock with same frequency as bit rate External Synchronous mode Internal External Outputs clock with frequency 16 times bit rate Outputs serial clock Inputs serial clock bit 7 bit 1 bit 0 COM CKE1 CKE0 Mode 0 0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 Asynchronous mode Reserved (Do not specify these combinations) 268 3. Interrupts and continuous transmission/reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10-13. Table 10-13 Transmit/Receive Interrupts Interrupt Flags RXI RDRF RIE Interrupt Request Conditions When serial reception is performed normally and receive data is transferred from RSR to RDR, bit RDRF is set to 1, and if bit RIE is set to 1 at this time, RXI is enabled and an interrupt is requested. (See figure 10-7 (a).) When TSR is found to be empty (on completion of the previous transmission) and the transmit data placed in TDR is transferred to TSR, bit TDRE is set to 1. If bit TIE is set to 1 at this time, TXI is enabled and an interrupt is requested. (See figure 10-7 (b).) When the last bit of the character in TSR is transmitted, if bit TDRE is set to 1, bit TEND is set to 1. If bit TEIE is set to 1 at this time, TEI is enabled and an interrupt is requested. (See figure 10-7 (c).) Notes The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0. Continuous reception can be performed by repeating the above operations until reception of the next RSR data is completed. The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0. Continuous transmission can be performed by repeating the above operations until the data transferred to TSR has been transmitted. TXI TDRE TIE TEI TEND TEIE TEI indicates that the next transmit data has not been written to TDR when the last bit of the transmit character in TSR is sent. 269 RDR RDR RSR (reception in progress) RXD pin RDRF = 0 RXD pin RSR (reception completed, transfer) RDRF 1 (RXI request when RIE = 1) Figure 10-7 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmission in progress) TXD pin TDRE = 0 TXD pin TSR (transmission completed, transfer) TDRE 1 (TXI request when TIE = 1) Figure 10-7 (b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmission in progress) TXD pin TEND = 0 TXD pin TSR (reception completed) TEND 1 (TEI request when TEIE = 1) Figure 10-7 (c) TEND Setting and TEI Interrupt 270 10.3.4 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 1. Data transfer format The general data transfer format in asynchronous communication is shown in figure 10-8. (LSB) Serial data Start bit Transmit/receive data (MSB) Parity bit Stop bit(s) 1 Mark state 1 bit 7 or 8 bits 1 bit or none 1 or 2 bits One transfer data unit (character or frame) Figure 10-8 Data Format in Asynchronous Communication In asynchronous communication, the communication line is normally in the mark state (high level). SCI3 monitors the communication line and when it detects a space (low level), identifies this as a start bit and begins serial data communication. One transfer data character consists of a start bit (low level), followed by transmit/receive data (LSB-first format, starting from the least significant bit), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, synchronization is performed by the falling edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. 271 Table 10-14 shows the 12 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10-14 Data Transfer Formats (Asynchronous Mode) SMR CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 * * * * MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 Serial Data Transfer Format and Frame Length 1 S S S S S S S S S S S S 2 3 4 5 6 7 8 9 10 11 12 STOP 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP STOP STOP P STOP P STOP STOP STOP STOP P STOP P STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP * Dont' care Notation: Start bit S: STOP: Stop bit Parity bit P: MPB: Multiprocessor bit 272 2. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection. When an external clock is input to the SCK3 pin, the input clock frequency should be 16 times the bit rate used. When SCI3 operates on an internal clock, the clock can be output at the SCK3 pin. In this case the frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises at the center of each bit of transmit/receive data, as shown in figure 10-9. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (1 frame) Figure 10-9 Phase Relationship between Output Clock and Transfer Data (Asynchronous Mode) (8-bit data, parity, 2 stop bits) 3. * Data transfer operations SCI3 initialization Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then SCI3 must be initialized as follows. Note: If the operation mode or data transfer format is changed, bits TE and RE must first be cleared to 0. When bit TE is cleared to 0, bit TDRE is set to 1. Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained when RE is cleared to 0. When an external clock is used in asynchronous mode, the clock should not be stopped during operation, including initialization. When an external clock is used in synchronous mode, the clock should not be supplied during operation, including initialization. 273 Figure 10-10 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Set data transfer format in SMR 1. Set clock selection in SCR3. Be sure to clear the other bits to 0. If clock output is selected in asynchronous mode, the clock is output immediately after setting bits CKE1 and CKE0. If clock output is selected for reception in synchronous mode, the clock is output immediately after bits CKE1, CKE0, and RE are set to 1. 2. Set the data transfer format in the serial mode register (SMR). Wait No 3. Write the value corresponding to the transfer rate in BRR. This operation is not necessary when an external clock is selected. 4. Wait for at least one bit period, then set bits TIE, RIE, MPIE, and TEIE in SCR3, and set bits TXD and TE or RE to 1 in PMR7. Setting bits TE and RE enables the TXD and RXD pins to be used. In asynchronous mode the mark state is established when transmitting, and the idle state waiting for a start bit when receiving. 3 Set value in BRR Has 1-bit period elapsed? Yes Set bits TIE, RIE, MPIE, and TEIE in SCR3, and set bits TXD and TE or RE to 1 in PMR7 4 End Figure 10-10 Example of SCI3 Initialization Flowchart 274 * Transmitting Figure 10-11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data to TDR 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 2 Continue data transmission? No Read bit TEND in SSR Yes 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TXD in PMR7 and bit TE in SCR3 to 0. TEND = 1? Yes 3 No Break output? Yes Set PDR = 0, PCR = 1 No Clear bit TE to 0 in SCR3 End Figure 10-11 Example of Data Transmission Flowchart (Asynchronous Mode) 275 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10-14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, 1 is set in TEND in SSR, and the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10-12 shows an example of the operation when transmitting in asynchronous mode. Start bit Serial data 1 0 D0 D1 Transmit data D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 1 frame D7 Parity Stop bit bit 0/1 1 Mark state 1 TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request Figure 10-12 Example of Operation when Transmitting in Asynchronous Mode (8-bit data, parity, 1 stop bit) 276 * Receiving Figure 10-13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bits OER, PER, FER in SSR OER + PER + FER = 1? No 2 Read receive data in SSR Yes 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the stop bit of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically. RDRF = 1? Yes Read receive data in RDR No 4 Receive error processing 3 Continue data reception? No Yes (A) Clear bit RE to 0 in SCR3 End Figure 10-13 Example of Data Reception Flowchart (Asynchronous Mode) 277 4 Start receive error processing Overrun error processing OER = 1? No FER = 1? No PER = 1? No Clear bits OER, PER, FER to 0 in SSR Parity error processing Yes Framing error processing Yes Yes Break? No 4. If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Yes Reception cannot be resumed if any of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD pin. (A) End of receive error processing Figure 10-13 Example of Data Reception Flowchart (Asynchronous Mode) (cont) 278 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10-14. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks. * Parity check SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit PM in the serial mode register (SMR). * Stop bit check SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked. * Status check SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. Table 10-15 shows the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Table 10-15 Receive Error Detection Conditions and Receive Data Processing Receive Error Abbreviation Detection Conditions Overrun error OER When the next date receive operation is completed while bit RDRF is still set to 1 in SSR When the stop bit is 0 Receive Data Processing Receive data is not transferred from RSR to RDR Framing error Parity error FER PER Receive data is transferred from RSR to RDR When the parity (odd or even) Receive data is transferred from set in SMR is different from RSR to RDR that of the received data 279 Figure 10-14 shows an example of the operation when receiving in asynchronous mode. Start bit Serial data 1 0 D0 D1 Receive data D7 1 frame Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark state (idle state) 1 RDRF FER LSI operation User processing RXI request RDRF cleared to 0 RDR data read 0 stop bit detected ERI request in response to framing error Framing error processing Figure 10-14 Example of Operation when Receiving in Asynchronous Mode (8-bit data, parity, 1 stop bit) 10.3.5 Operation in Synchronous Mode In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. SCI3 has separate transmission and reception units, allowing full-duplex communication with a shared clock. As the transmission and reception units are both double-buffered, data can be written during transmission and read during reception, making possible continuous transmission and reception. 280 1. Data transfer format The general data transfer format in asynchronous communication is shown in figure 10-15. * Serial clock LSB Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 * Don't care 8 bits One transfer data unit (character or frame) Don't care Note: High level except in continuous transmission/reception Figure 10-15 Data Format in Synchronous Communication In synchronous communication, data on the communication line is output from one falling edge of the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of the serial clock. One transfer data character begins with the LSB and ends with the MSB. After output of the MSB, the communication line retains the MSB state. When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial clock. The data transfer format uses a fixed 8-bit data length. Parity and multiprocessor bits cannot be added. 2. Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK3 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10-12 for details on clock source selection. When SCI3 operates on an internal clock, the serial clock is output at the SCK3 pin. Eight pulses of the serial clock are output in transmission or reception of one character, and when SCI3 is not transmitting or receiving, the clock is fixed at the high level. 281 3. * Data transfer operations SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in 10.3.4, 3. SCI3 initialization, and shown in figure 10-10. * Transmitting Figure 10-16 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically, the clock is output, and data transmission is started. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 1 Read bit TDRE in SSR No TDRE = 1? Yes Write transmit data to TDR 2 Continue data transmission? No Read bit TEND in SSR Yes TEND = 1? Yes Clear bit TE to 0 in SCR3 No End Figure 10-16 Example of Data Transmission Flowchart (Synchronous Mode) 282 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is selected, data is output in synchronization with the input clock. Serial data is transmitted from the TXD pin in order from the LSB (bit 0) to the MSB (bit 7). When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. After transmission ends, the SCK3 pin is fixed at the high level. Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data reception status is set to 1. Check that these error flags are all cleared to 0 before a transmit operation. Figure 10-17 shows an example of the operation when transmitting in synchronous mode. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND TXI request LSI operation User processing TDRE cleared to 0 Data written to TDR TXI request 1 frame TEI request Figure 10-17 Example of Operation when Transmitting in Synchronous Mode 283 * Receiving Figure 10-18 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start 1 Read bit OER in SSR 1. Read bit OER in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Yes 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. When the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Reception cannot be resumed if bit OER is set to 1. Overrun error processing OER = 1? No 2 Read bit RDRF in SSR RDRF = 1? Yes Read receive data in RDR No 4 3 Continue data reception? No Clear bit RE to 0 in SCR3 Yes 4 Start overrun error processing End Overrun error processing Clear bit OER to 0 in SSR End of overrun error processing Figure 10-18 Example of Data Reception Flowchart (Synchronous Mode) 284 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR. If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies an overrun error, bit OER is set to 1. Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested. See table 10-15 for the conditions for detecting a receive error, and receive data processing. Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER, PER, and RDRF must therefore be cleared to 0 before resuming reception. Figure 10-19 shows an example of the operation when receiving in synchronous mode. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame RDRF OER LSI operation User processing RXI request RDRF cleared to 0 RDR data read RXI request 1 frame ERI request in response to overrun error RDR data has not been read (RDRF = 1) Overrun error processing Figure 10-19 Example of Operation when Receiving in Synchronous Mode 285 * Simultaneous transmit/receive Figure 10-20 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start 1 Read bit TDRE in SSR TDRE = 1? Yes Write transmit data to TDR No 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR. When the RDR data is read, bit RDRF is cleared to 0 automatically. 3. When continuing data transmission/reception, finish reading of bit RDRF and RDR before receiving the MSB (bit 7) of the current frame. Before receiving the MSB (bit 7) of the current frame, also read TDRE = 1 to confirm that a write can be performed, then write data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically, and when the data in RDR is read, bit RDRF is cleared to 0 automatically. 4. If an overrun error has occurred, read bit OER in SSR, and after carrying out the necessary error processing, clear bit OER to 0. Transmission/ reception cannot be resumed if bit OER is set to 1. See figure 10-18 for details on overrun error processing. Read bit OER in SSR OER = 1? No Read bit RDRF in SSR Yes 2 RDRF = 1? Yes Read receive data in RDR No 4 Overrun error processing 3 Continue data transmission/reception? No Clear bits TE and RE to 0 in SCR3 Yes End Figure 10-20 Example of Simultaneous Data Transmission/Reception Flowchart(Synchronous Mode) 286 Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1. 2. When switching from reception to simultaneous transmission/reception, check that SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1. 10.3.6 Multiprocessor Communication Function The multiprocessor communication function enables data to be exchanged among a number of processors on a shared communication line. Serial data communication is performed in asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the transfer data). In multiprocessor communication, each receiver is assigned its own ID code. The serial communication cycle consists of two cycles, an ID transmission cycle in which the receiver is specified, and a data transmission cycle in which the transfer data is sent to the specified receiver. These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID transmission cycle, and 0, a data transmission cycle. The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it compares the ID code with its own ID code, and if they are the same, receives the transfer data sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor bit set to 1 is sent again. In this way, a number of processors can exchange data among themselves. Figure 10-21 shows an example of communication between processors using the multiprocessor format. 287 Sender Communication line Receiver A (ID = 01) Receiver B (ID = 02) Receiver C (ID = 03) Receiver D (ID = 04) Serial data H'01 (MPB = 1) ID transmission cycle (specifying the receiver) H'AA (MPB = 0) Data transmission cycle (sending data to the receiver specified buy the ID) MPB: Multiprocessor bit Figure 10-21 Example of Inter-Processor Communication Using Multiprocessor Format (Sending data H'AA to receiver A) There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity bit specification is invalid. See table 10-14 for details. For details on the clock used in multiprocessor communication, see 10.3.4, Operation in Synchronous Mode. * Multiprocessor data transmitting Figure 10-22 shows an example of a flowchart for multiprocessor data transmission. This procedure should be followed for multiprocessor data transmission after initializing SCI3. 288 Start 1 Read bit TDRE in SSR TDRE = 1? Yes Set bit MPBT in SSR No 1. Read the serial status register (SSR) and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR). When data is written to TDR, bit TDRE is cleared to 0 automatically. 2. When continuing data transmission, be sure to read TDRE = 1 to confirm that a write can be performed before writing data to TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. 3. If a break is to be output when data transmission ends, set the port PCR to 1 and clear the port PDR to 0, then clear bit TE in SCR3 to 0. Write transmit data to TDR 2 Continue data transmission? No Read bit TEND in SSR Yes TEND = 1? Yes No 3 Break output? Yes No Set PDR = 0, PCR = 1 Clear bit TE to 0 in SCR3 End Figure 10-22 Example of Multiprocessor Data Transmission Flowchart 289 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10-14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit TDRE is set to 1, 1 is set in TEND in SSR, and the mark state, in which 1s are transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI request is made. Figure 10-23 shows an example of the operation when transmitting using the multiprocessor format. Start bit Serial data 1 0 D0 D1 Transmit data D7 1 frame MPB 0/1 Stop Start bit bit 1 0 D0 Transmit data D1 1 frame MPB 0/1 Stop bit 1 Mark state 1 D7 TDRE TEND LSI TXI request operation User processing TDRE cleared to 0 Data written to TDR TXI request TEI request Figure 10-23 Example of Operation when Transmitting Using Multiprocessor Format (8-bit data, multiprocessor bit, 1 stop bit) * Multiprocessor receiving Figure 10-24 shows an example of a flowchart for multiprocessor data reception. This procedure should be followed for multiprocessor data reception after initializing SCI3. 290 Start 1. Set bit MPIE to 1 in SCR3. 2. Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. 3. Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR and compare it with this receiver's own ID. If the ID is not this receiver's, set bit MPIE to 1 again. When the RDR data is read, bit RDRF is cleared to 0 automatically. 4. Read SSR and check that bit RDRF is set to 1, then read the data in RDR. 5. If a receive error has occurred, read bits OER and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER and FER are both cleared to 0. Reception cannot be resumed if either of these bits is set to 1. In the case of a framing error, a break can be detected by reading the value of the RXD pin. 1 Set bit MPIE to 1 in SCR3 2 Read bits OER and FER in SSR Yes OER + FER = 1? No 3 Read bit RDRF in SSR RDRF = 1? Yes Read receive data in RDR No Own ID? Yes Read bits OER and FER in SSR No OER + FER = 1? No 4 Read bit RDRF in SSR Yes RDRF = 1? Yes Read receive 4 data in RDR No 5 Receive error processing Continue data reception? No Clear bit RE to 0 in SCR3 End Yes (A) Figure 10-24 Example of Multiprocessor Data Reception Flowchart 291 Start receive error processing Overrun error processing OER = 1? No FER = 1? No Clear bits OER and FER to 0 in SSR Yes Yes Yes Break? No Framing error processing End of receive error processing (A) Figure 10-24 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10-25 shows an example of the operation when receiving using the multiprocessor format. 292 Start bit Serial data 1 0 D0 Receive data (ID1) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data1) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 RDR data read When data is not this receiver's ID, bit MPIE is set to 1 again ID1 No RXI request RDR retains previous state (a) When data does not match this receiver's ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 1 frame D7 MPB 1 Stop Start bit bit 1 0 D0 Receive data (Data2) D1 1 frame D7 MPB 0 Stop bit 1 Mark state (idle state) 1 MPIE RDRF RDR value LSI operation User processing ID1 ID2 Data2 RXI request MPIE cleared to 0 RDRF cleared to 0 RDR data read RXI request RDRF cleared to 0 RDR data read Bit MPIE set to 1 again When data is this receiver's ID, reception is continued (b) When data matches this receiver's ID Figure 10-25 Example of Operation when Receiving using Multiprocessor Format (8-bit data, multiprocessor bit, 1 stop bit) 293 10.3.7 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10-16. Table 10-16 SCI3 Interrupt Requests Interrupt Abbreviation RXI TXI TEI ERI Interrupt Request Interrupt request initiated by receive data full flag (RDRF) Interrupt request initiated by transmit data empty flag (TDRE) Interrupt request initiated by transmit end flag (TEND) Interrupt request initiated by receive error flag (OER, FER, PER) Vector Address H'0024 Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3. When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in SSR, a TEI interrupt is requested. These two interrupts are generated during transmission. The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI interrupt will be requested even if the transmit data is not ready. Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI interrupt will be requested even if the transmit data has not been sent. Effective use of these interrupt requests can be made by having processing that transfers transmit data to TDR carried out in the interrupt service routine. To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been transferred to TDR. When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during reception. For further details, see 3.3, Interrupts. 294 10.3.8 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR once only (not two or more times). 2. Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the states shown in table 10-17. If an overrun error is detected, data transfer from RSR to RDR will not be performed, and the receive data will be lost. Table 10-17 SSR Status Flag States and Receive Data Transfer SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 x x x Receive Data Transfer RSR RDR Receive Error Status x Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. x : Receive data is not transferred from RSR to RDR. Note: * Bit RDRF retains its state prior to data reception. 295 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD pin directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4. Mark state and break detection When bit TE is cleared to 0, the TXD pin functions as an I/O port whose input/output direction and level are determined by PDR and PCR. This fact can be used to set the TXD pin to the mark state, or to detect a break during transmission. To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and PDR = 1. Since bit TE is cleared to 0 at this time, the TXD pin functions as an I/O port and 1 is output. To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0. When bit TE is cleared to 0, the transmission unit is initialized regardless of the current transmission state, the TXD pin functions as an I/O port, and 0 is output from the TXD pin. 5. Receive error flags and transmit operation (synchronous mode only) When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0. 6. Receive data sampling timing and receive margin in asynchronous mode In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate. When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock. This is illustrated in figure 10-26. 296 16 clock pulses 8 clock pulses 0 7 15 0 7 15 0 Internal basic clock Receive data (RXD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 10-26 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). M ={(0.5 -- where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in equation (1), a receive margin of 46.875% is given by equation (2). When D = 0.5 and F = 0, M = {0.5 -- 1/(2 ! 16)} ! 100 [%] = 46.875% ..... Equation (2) However, this is only a computed value, and a margin of 20% to 30% should be allowed when carrying out system design. 1 D -- 0.5 -- (L -- 0.5) F} ! 100 [%] )-- 2N N ..... Equation (1) 297 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR is read more than once, the second and subsequent read operations will be performed while bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. This is illustrated in figure 10-27. Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 Data 3 (A) RDR read (B) RDR read Data 1 is read at point (A) Data 2 is read at point (B) Figure 10-27 Relation between RDR Read Timing and Data In this case, only a single RDR read operation (not two or more) should be performed after first checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is sufficient margin in an RDR read operation before reception of the next frame is completed. To be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in synchronous mode, or before the STOP bit is transferred in asynchronous mode. 298 Section 11 14-Bit PWM 11.1 Overview The H8/3657 Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a D/A converter by connecting a low-pass filter. 11.1.1 Features Features of the 14-bit PWM are as follows. * Choice of two conversion periods A conversion period of 32,768/o, with a minimum modulation width of 2/o or a conversion period of 16,384/o, with a minimum modulation width of 1/o can be chosen. * Pulse division method for less ripple 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the 14-bit PWM. PWDRL o/2 o/4 PWM waveform generator PWCR PWM Notation: PWDRL: PWM data register L PWDRU: PWM data register U PWCR: PWM control register Figure 11-1 Block Diagram of the 14 bit PWM 299 Internal data bus PWDRU 11.1.3 Pin Configuration Table 11-1 shows the output pin assigned to the 14-bit PWM. Table 11-1 Pin Configuration Name PWM output pin Abbrev. PWM I/O Output Function Pulse-division PWM waveform output 11.1.4 Register Configuration Table 11-2 shows the register configuration of the 14-bit PWM. Table 11-2 Register Configuration Name PWM control register PWM data register U PWM data register L Abbrev. PWCR PWDRU PWDRL R/W W W W Initial Value H'FE H'C0 H'00 Address H'FFD0 H'FFD1 H'FFD2 300 11.2 Register Descriptions 11.2.1 PWM Control Register (PWCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 PWCR0 0 W PWCR is an 8-bit write-only register for input clock selection. Upon reset, PWCR is initialized to H'FE. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. Bit 0: Clock select 0 (PWCR0) Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1. Bit 0 PWCR0 Description 0 1 The input clock is o/2 (to = 2/o). The conversion period is 16,384/o, with a minimum modulation width of 1/o. (initial value) The input clock is o/4 (to = 4/o). The conversion period is 32,768/o, with a minimum modulation width of 2/o. Notation: to: Period of PWM input clock 301 11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) PWDRU Bit Initial value Read/Write PWDRL Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle. When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should always be written in the following sequence: 1. 2. Write the lower 8 bits to PWDRL. Write the upper 6 bits to PWDRU. PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1. Upon reset, PWDRU and PWDRL are initialized to H'C000. 302 11.3 Operation When using the 14-bit PWM, set the registers in the following sequence. 1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P14/PWM is designated for PWM output. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32,768/o (PWCR0 = 1) or 16,384/o (PWCR0 = 0). Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data in these registers will be latched in the PWM waveform generator, updating the PWM waveform generation in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 11-2. The total of the highlevel pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be represented as follows. TH = (data value in PWDRU and PWDRL + 64) x to/2 where to is the PWM input clock period, either 2/o (bit PWCR0 = 0) or 4/o (bit PWCR0 = 1). Example: Settings in order to obtain a conversion period of 8,192 s: When bit PWCR0 = 0, the conversion period is 16,384/o, so o must be 2 MHz. In this case tfn = 128 s, with 1/o (resolution) = 0.5 s. When bit PWCR0 = 1, the conversion period is 32,768/o, so o must be 4 MHz. In this case tfn = 128 s, with 2/o (resolution) = 0.5 s. Accordingly, for a conversion period of 8,192 s, the system clock frequency (o) must be 2 MHz or 4 MHz. 2. 3. 303 1 conversion period t f1 t f2 t f63 t f64 t H1 t H2 t H3 t H63 t H64 TH = t H1 + t H2 + t H3 + ..... t H64 t f1 = t f2 = t f3 ..... = t f84 Figure 11-2 PWM Output Waveform 304 Section 12 A/D Converter 12.1 Overview The H8/3657 Series includes on-chip a resistance-ladder-based successive-approximation analog-todigital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. * * * * * * 8-bit resolution Eight input channels Conversion time: approx. 12.4 s per channel (at 5 MHz operation) Built-in sample-and-hold function Interrupt requested on completion of A/D conversion A/D conversion can be started by external trigger input 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the A/D converter. ADTRG AMR AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 AVCC + Comparator - Control logic AVCC Reference voltage AVSS AVSS ADRR Notation: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register Figure 12-1 Block Diagram of the A/D Converter 305 Internal data bus IRRAD Multiplexer ADSR 12.1.3 Pin Configuration Table 12-1 shows the A/D converter pin configuration. Table 12-1 Pin Configuration Name Analog power supply Analog ground Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 External trigger input Abbrev. AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Function Power supply and reference voltage of analog part Ground and reference voltage of analog part Analog input channel 0 Analog input channel 1 Analog input channel 2 Analog input channel 3 Analog input channel 4 Analog input channel 5 Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion 12.1.4 Register Configuration Table 12-2 shows the A/D converter register configuration. Table 12-2 Register Configuration Name A/D mode register A/D start register A/D result register Abbrev. AMR ADSR ADRR R/W R/W R/W R Initial Value H'30 H'7F Not fixed Address H'FFC4 H'FFC6 H'FFC5 306 12.2 Register Descriptions 12.2.1 A/D Result Register (ADRR) Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R 2 ADR2 R 1 ADR1 R 0 ADR0 R Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 12.2.2 A/D Mode Register (AMR) Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'30. Bit 7: Clock select (CKS) Bit 7 sets the A/D conversion speed. Bit 7 CKS 0 1 Conversion Time Conversion Period 62/o (initial value) 31/o o = 2 MHz 31 s 15.5 s o = 5 MHz 12.4 s * Note: * Operation is not guaranteed if the conversion time is less than 12.4 s. Set bit 7 for a value of at least 12.4 s. 307 Bit 6: External trigger select (TRGE) Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6 TRGE 0 1 Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger (ADTRG) edge is selected by bit INTEG5 of IEGR2. See 3.3.2 for details. Bits 5 and 4: Reserved bits Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. Bits 3 to 0: Channel select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 CH3 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 CH2 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 CH1 * 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel No channel selected AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved (initial value) Note: * Don't care 308 12.2.3 A/D Start Register (ADSR) Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7: A/D start flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF 0 Description Read: Indicates the completion of A/D conversion Write: Stops A/D conversion 1 Read: Indicates A/D conversion in progress Write: Starts A/D conversion (initial value) Bits 6 to 0: Reserved bits Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 309 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 Start of A/D Conversion by External Trigger Input The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit INTEG5 of interrupt edge select register 2 (IEGR2) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12-2 shows the timing. o Pin ADTRG (when bit INTEG5 = 0) ADSF A/D conversion Figure 12-2 External Trigger Input Timing 310 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see 3.3, Interrupts. 12.5 Typical Use An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as the analog input channel. Figure 12-3 shows the operation timing. 1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. Bit IENAD = 1, so an A/D conversion end interrupt is requested. The A/D interrupt handling routine starts. The A/D conversion result is read and processed. The A/D interrupt handling routine ends. 2. 3. 4. 5. 6. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12-4 and 12-5 show flow charts of procedures for using the A/D converter. 311 Interrupt (IRRAD) Set * IENAD ADSF A/D conversion starts Set * Set * Figure 12-3 Typical A/D Converter Operation Timing 312 Idle A/D conversion (1) Idle A/D conversion result (1) Channel 1 (AN 1) operation state A/D conversion (2) Idle Read conversion result Read conversion result A/D conversion result (2) Conversion result is reset when next conversion starts ADRR Note: * ( ) indicates instruction execution by software. Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 12-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) 313 Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRR data Yes Perform A/D conversion? No End Figure 12-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes * Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. * 314 Section 13 Electrical Characteristics 13.1 Absolute Maximum Ratings Table 13-1 lists the absolute maximum ratings. Table 13-1 Absolute Maximum Ratings Item Power supply voltage Analog power supply voltage Programming voltage Input voltage Ports other than Port B Port B Operating temperature Storage temperature Topr Tstg Symbol VCC AVCC VPP Vin Value -0.3 to +7.0 -0.3 to +7.0 -0.3 to +13.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -20 to +75 -55 to +125 Unit V V V V V C C Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 315 13.2 Electrical Characteristics 13.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. 1. Power supply voltage vs. oscillator frequency range 10.0 f OSC (MHz) 32.768 5.0 fw (kHz) 2.2* 2.7 2.0 4.0 5.5 VCC (V) 2.2 * 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode (high speed) * All operating modes Note: * The oscillation start voltage is 2.5 V. 316 2. Power supply voltage vs. clock frequency range 5.0 oSUB (kHz) 2.2 2.7 4.0 5.5 VCC (V) 16.384 o (MHz) 2.5 8.192 4.096 0.5 2.2 4.0 5.5 VCC (V) * Active (high speed) mode * Sleep (high speed) mode (except CPU) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 78.125 o (kHz) 39.0625 7.8125 2.7 4.0 5.5 VCC (V) * Active (medium speed) mode * Sleep (medium speed) mode (except CPU) 3. Analog power supply voltage vs. A/D converter operating range 5.0 o (MHz) 2.5 Don't use in these modes. * Active (medium speed) mode * Sleep (medium speed) mode 0.5 2.2 2.7 4.0 4.5 5.5 AVCC (V) * Active (high speed) mode * Sleep (high speed) mode 317 13.2.2 DC Characteristics (HD6473657) Table 13-2 lists the DC characteristics of the HD6473657. Table 13-2 DC Characteristics VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Input high voltage Symbol VIH Applicable Pins RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 PB0 to PB7 OSC1 Note: Connect the TEST pin to VSS. Min 0.9 VCC Typ -- Max VCC + 0.3 Unit V Test Condition Notes 0.8 VCC -- VCC + 0.3 V 0.8 VCC -- AVCC + 0.3 VCC + 0.3 VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC - 0.5 -- VCC - 0.3 -- 318 Table 13-2 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Input low voltage Symbol VIL Applicable Pins RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 Min -0.3 Typ -- Max 0.1 VCC Unit V Test Condition Notes -0.3 -- 0.2 VCC V -0.3 -0.3 -- -- 0.5 0.3 V VCC = 4.0 V to 5.5 V 319 Table 13-2 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Output high voltage Symbol VOH Applicable Pins P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 OSC1, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 PB0 to PB7 Input leakage current Pull-up MOS current | IIL | RES, IRQ0 Min Typ Max -- -- -- Unit V Test Condition VCC = 4.0 V to 5.5 V -IOH = 1.0 mA VCC = 4.0 V to 5.5 V -IOH = 0.5 mA -IOH = 0.1 mA Notes VCC - 1.0 -- VCC - 0.5 -- VCC - 0.4 -- Output low voltage VOL -- -- 0.6 V VCC = 4.0 V to 5.5 V IOL = 1.6 mA -- -- 0.4 IOL = 0.4 mA Input/ output leakage current | IIL | -- -- 1 A Vin = 0.5 V to (VCC - 0.5 V) -- -- -- -- 1 20 A Vin = 0.5 V to AVCC - 0.5 V Vin = 0.5 V to (VCC - 0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.7 V, Vin = 0 V Reference value -Ip P10 to P17, P30 to P35, P50 to P57 50 -- -- 25 300 -- A 320 Table 13-2 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Symbol Applicable Pins All input pins except RES RES IRQ0 Active IOPE1 mode current dissipation VCC Min -- Typ -- Max 15 Unit pF Test Condition f = 1 MHz, Vin = 0 V, Ta = 25C Notes Input Cin capacitance -- -- -- -- -- -- -- 10 5 2 1.5 60 30 15 -- -- 2.5 mA mA Active (high-speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz VCC = 2.2 V, fOSC = 5 MHz 1, 2 1, 2 Reference value IOPE2 VCC -- Active (medium-speed) mode 1, 2 VCC = 5 V, fOSC = 10 MHz (o OSC/128) VCC = 2.7 V, fOSC = 10 MHz (o OSC/128) VCC = 2.2 V, fOSC = 5 MHz (o OSC/128) 1, 2 Reference value -- -- Sleep ISLEEP1 mode current dissipation VCC -- -- -- ISLEEP2 VCC -- 0.8 0.4 4.5 2.2 0.9 1.4 -- -- 6.5 -- -- 2.4 mA mA Sleep (high-speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz VCC = 2.2 V, fOSC = 5 MHz 1, 2 1, 2 Reference value Sleep (medium-speed) mode 1, 2 VCC = 5 V, fOSC = 10 MHz (o OSC/128) VCC = 2.7 V, fOSC = 10 MHz (o OSC/128) VCC = 2.2 V, fOSC = 5 MHz (o OSC/128) 1, 2 Reference value -- -- Subactive ISUB mode current dissipation VCC -- 0.7 0.4 20 -- -- 30 A VCC = 2.7 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/8) 1, 2 -- 15 -- 1, 2 Reference value -- 9 -- 321 Table 13-2 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Symbol Applicable Pins VCC Min -- Typ 10 Max 20 Unit A Test Condition VCC = 2.7 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/2) A VCC = 2.7 V 32-kHz crystal oscillator VCC = 2.2 V 32-kHz crystal oscillator A 32-kHz crystal oscillator not used Notes 1, 2 Subsleep ISUBSP mode current dissipation -- 7 -- 1, 2 Reference value 1, 2 1, 2 Reference value 1, 2 Watch IWATCH mode current dissipation VCC -- -- 7.5 6 9 -- Standby ISTBY mode current dissipation RAM data retaining voltage VRAM VCC -- -- 5 VCC 2 -- -- V Notes: 1. Pin states during current measurement are given below. 2. Excludes current in pull-up MOS transistors and output buffers. Mode Active (high-speed) mode Active (medium-speed) mode Sleep (high-speed) mode Sleep (medium-speed) mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC RES Pin VCC Internal State Operates Operates (oOSC/128) Only timers operate Only timers operate (oOSC/128) Operates Only timers operate, CPU stops VCC VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal VCC Other Pins VCC Oscillator Pins System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC Only time base VCC operates, CPU stops CPU and timers both stop VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 322 Table 13-2 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated. Values Item Allowable output low current (per pin) Allowable output low current (total) All output pins Symbol IOL IOL -IOH -IOH Min -- -- All output pins -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- Max 2 0.5 40 20 2 0.2 15 10 mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V Unit mA Test Condition VCC = 4.0 V to 5.5 V Allowable output All output pins high current (per pin) Allowable output high current (total) All output pins 323 13.2.3 AC Characteristics (HD6473657) Table 13-3 lists the control signal timing, and tables 13-4 and 13-5 list the serial interface timing of the HD6473657. Table 13-3 Control Signal Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Applicable Pins OSC1, OSC2 OSC1, OSC2 Values Min Typ 2 2 -- -- Max 10 5 1000 ns 1000 128 25.5 tOSC s kHz s tW tcyc tsubcyc ms VCC = 4.0 V to 5.5 V VCC = 2.5 V to 5.5 V ms VCC = 4.0 V to 5.5 V VCC = 2.5 V to 5.5 V s ns VCC = 2.5 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13-2 Figure 13-1 2 VCC = 2.7 V to 5.5 V 1 Figure 13-1 1 Unit MHz Test Condition VCC = 2.7 V to 5.5 V Reference Figure System clock fOSC oscillation frequency OSC clock (oOSC) cycle time System clock (o) cycle time Subclock oscillation frequency Watch clock (oW) cycle time Subclock (oSUB) cycle time Instruction cycle time Oscillation stabilization time (crystal oscillator) Oscillation stabilization time (ceramic oscillator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width tREL trc tOSC tcyc fW tW tsubcyc 100 -- 200 -- 2 -- -- -- X1, X2 X1, X2 -- -- 2 2 32.768 -- 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 -- 40 60 20 40 2 -- -- -- -- 15 20 15 20 -- OSC1, OSC2 -- -- trc OSC1, OSC2 -- -- trc tCPH tCPL tCPr tCPf X1, X2 OSC1 OSC1 -- 40 80 40 80 -- -- -- -- ns Figure 13-1 ns ns RES 18 tcyc tsubcyc Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 324 Table 13-3 Control Signal Timing (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Oscillation start voltage Input pin high width Symbol Vstart tIH Applicable Pins OSC1, OSC2 X1, X2 IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV Values Min Typ 2.5 2.5 2 -- -- -- Max -- -- -- tcyc tsubcyc Figure 13-3 Unit V Test Condition Reference Figure Input pin low width tIL 2 -- -- tcyc tsubcyc Figure 13-3 325 Table 13-4 Serial Interface (SCI1) Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tscyc tSCKH tSCKL tSCKr tSCKf tSOD tSIS tSIH Applicable Pins SCK1 SCK1 SCK1 SCK1 SCK1 SO1 SI1 SI1 Values Min Typ 4 0.4 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 60 80 60 80 200 350 -- -- -- -- ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V Unit tcyc tscyc tscyc ns VCC = 4.0 V to 5.5 V Test Condition Reference Figure Figure 13-4 200 -- 400 -- 200 -- 400 -- Table 13-5 Serial Interface (SCI3) Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Values Item Input clock cycle Asynchronous Synchronous tSCKW tTXD tRXS tRXH Symbol tscyc Min 4 6 0.4 -- -- 200 400 200 400 Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 13-6 ns VCC = 4.0 V to 5.5 V Figure 13-6 tscyc tcyc VCC = 4.0 V to 5.5 V Figure 13-5 Figure 13-6 Unit tcyc Test Conditions Reference Figure Figure 13-5 Input clock pulse width Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) 326 13.2.4 DC Characteristics (HD6433657, HD6433656, HD6433655, HD6433654, HD6433653, HD6433652) Table 13-6 lists the DC characteristics of the HD6433657, the HD6433656, the HD6433655, the HD6433654, the HD6433653, and the HD6433652. Table 13-6 DC Characteristics VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Input high voltage Symbol VIH Applicable Pins RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 PB0 to PB7 OSC1 Note: Connect the TEST pin to VSS. Min 0.9 VCC Typ -- Max VCC + 0.3 Unit V Test Condition Notes 0.8 VCC -- VCC + 0.3 V 0.8 VCC -- AVCC + 0.3 VCC + 0.3 VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC - 0.5 -- VCC - 0.3 -- 327 Table 13-6 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Input low voltage Symbol VIL Applicable Pins RES, INT0 to INT7, IRQ0 to IRQ3, ADTRG, TMIB, TMRIV, TMCIV, FTCI, FTIA, FTIB, FTIC, FTID, SCK1, SCK3, TRGV SI1, RXD, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94, PB0 to PB7 OSC1 Note: Connect the TEST pin to VSS. Min -0.3 Typ -- Max 0.1 VCC Unit V Test Condition Notes -0.3 -- 0.2 VCC V -0.3 -0.3 -- -- 0.5 0.3 V VCC = 4.0 V to 5.5 V 328 Table 13-6 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Output high voltage Symbol VOH Applicable Pins P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 OSC1, P10 to P17, P20 to P27, P30 to P35, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P94 PB0 to PB7 Input leakage current Pull-up MOS current | IIL | RES, IRQ0 Min Typ Max -- -- -- Unit V Test Condition VCC = 4.0 V to 5.5 V -IOH = 1.0 mA VCC = 4.0 V to 5.5 V -IOH = 0.5 mA -IOH = 0.1 mA Notes VCC - 1.0 -- VCC - 0.5 -- VCC - 0.4 -- Output low voltage VOL -- -- 0.6 V VCC = 4.0 V to 5.5 V IOL = 1.6 mA -- -- 0.4 IOL = 0.4 mA Input/ output leakage current | IIL | -- -- 1 A Vin = 0.5 V to (VCC - 0.5 V) -- -- -- -- 1 1 A Vin = 0.5 V to AVCC - 0.5 V Vin = 0.5 V to (VCC - 0.5 V) VCC = 5 V, Vin = 0 V VCC = 2.7 V, Vin = 0 V Reference value -Ip P10 to P17, P30 to P35, P50 to P57 50 -- -- 25 300 -- A 329 Table 13-6 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Symbol Applicable Pins All input pins except RES RES IRQ0 Active IOPE1 mode current dissipation VCC Min -- Typ -- Max 15 Unit pF Test Condition f = 1 MHz, Vin = 0 V, Ta = 25C Notes Input Cin capacitance -- -- -- -- -- -- -- 10 5 2 1.5 15 15 15 -- -- 2.5 mA mA Active (high-speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz VCC = 2.2 V, fOSC = 5 MHz 1, 2 1, 2 Reference value IOPE2 VCC -- Active (medium-speed) mode 1, 2 VCC = 5 V, fOSC = 10 MHz (o OSC/128) VCC = 2.7 V, fOSC = 10 MHz (o OSC/128) VCC = 2.2 V, fOSC = 5 MHz (o OSC/128) 1, 2 Reference value -- -- Sleep ISLEEP1 mode current dissipation VCC -- -- -- ISLEEP2 VCC -- 0.8 0.4 4.5 2.2 0.9 1.4 -- -- 6.5 -- -- 2.4 mA mA Sleep (high-speed) mode VCC = 5 V, fOSC = 10 MHz VCC = 2.7 V, fOSC = 10 MHz VCC = 2.2 V, fOSC = 5 MHz 1, 2 1, 2 Reference value Sleep (medium-speed) mode 1, 2 VCC = 5 V, fOSC = 10 MHz (o OSC/128) VCC = 2.7 V, fOSC = 10 MHz (o OSC/128) VCC = 2.2 V, fOSC = 5 MHz (o OSC/128) 1, 2 Reference value -- -- Subactive ISUB mode current dissipation VCC -- 0.7 0.4 20 -- -- 30 A VCC = 2.7 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/8) 1, 2 -- 15 -- 1, 2 Reference value -- 9 -- 330 Table 13-6 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C unless otherwise indicated. Values Item Symbol Applicable Pins VCC Min -- Typ 10 Max 20 Unit A Test Condition VCC = 2.7 V 32-kHz crystal oscillator (oSUB = oW/2) VCC = 2.2 V 32-kHz crystal oscillator (oSUB = oW/2) A VCC = 2.7 V 32-kHz crystal oscillator VCC = 2.2 V 32-kHz crystal oscillator A 32-kHz crystal oscillator not used Notes 1, 2 Subsleep ISUBSP mode current dissipation -- 7 -- 1, 2 Reference value 1, 2 1, 2 Reference value 1, 2 Watch IWATCH mode current dissipation VCC -- -- 7.5 6 9 -- Standby ISTBY mode current dissipation RAM data retaining voltage VRAM VCC -- -- 5 VCC 2 -- -- V Notes: 1. Pin states during current measurement are given below. 2. Excludes current in pull-up MOS transistors and output buffers. Mode Active (high-speed) mode Active (medium-speed) mode Sleep (high-speed) mode Sleep (medium-speed) mode Subactive mode Subsleep mode Watch mode Standby mode VCC VCC VCC VCC VCC RES Pin VCC Internal State Operates Operates (oOSC/128) Only timers operate Only timers operate (oOSC/128) Operates Only timers operate, CPU stops Only time base perates, CPU stops CPU and timers both stop VCC VCC VCC VCC System clock oscillator: ceramic or crystal Subclock oscillator: crystal VCC Other Pins VCC Oscillator Pins System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: ceramic or crystal Subclock oscillator: Pin X1 = VCC 331 Table 13-6 DC Characteristics (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise indicated. Values Item Allowable output low current (per pin) Allowable output low current (total) All output pins Symbol IOL IOL -IOH -IOH Min -- -- All output pins -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- Max 2 0.5 40 20 2 0.2 15 10 mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V Unit mA Test Condition VCC = 4.0 V to 5.5 V Allowable output All output pins high current (per pin) Allowable output high current (total) All output pins 332 13.2.5 AC Characteristics (HD6433657, HD6433656, HD6433655, HD6433654, HD6433653, HD6433652) Table 13-7 lists the control signal timing, and tables 13-8 and 13-9 list the serial interface timing of the HD6433657, the HD6433656, the HD6433655, the HD6433654, the HD6433653, and the HD6433652. Table 13-7 Control Signal Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Applicable Pins OSC1, OSC2 OSC1, OSC2 Values Min Typ 2 2 -- -- Max 10 5 1000 ns 1000 128 25.5 tOSC s kHz s tW tcyc tsubcyc ms VCC = 4.0 V to 5.5 V VCC = 2.5 V to 5.5 V ms VCC = 4.0 V to 5.5 V VCC = 2.5 V to 5.5 V s ns VCC = 2.5 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Figure 13-2 Figure 13-1 2 VCC = 2.7 V to 5.5 V 1 Figure 13-1 1 Unit MHz Test Condition VCC = 2.7 V to 5.5 V Reference Figure System clock fOSC oscillation frequency OSC clock (oOSC) cycle time System clock (o) cycle time Subclock oscillation frequency Watch clock (oW) cycle time Subclock (oSUB) cycle time Instruction cycle time Oscillation stabilization time (crystal oscillator) Oscillation stabilization time (ceramic oscillator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width trc tOSC tcyc fW tW tsubcyc 100 -- 200 -- 2 -- -- -- X1, X2 X1, X2 -- -- 2 2 32.768 -- 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 -- 40 60 20 40 2 -- -- -- -- 15 20 15 20 -- OSC1, OSC2 -- -- trc OSC1, OSC2 -- -- trc tCPH tCPL tCPr tCPf tREL X1, X2 OSC1 OSC1 -- 40 80 40 80 -- -- -- -- ns Figure 13-1 ns ns RES 18 tcyc tsubcyc Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 333 Table 13-7 Control Signal Timing (cont) VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Oscillation start voltage Input pin high width Symbol Vstart tIH Applicable Pins OSC1, OSC2 X1, X2 IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV IRQ0 to IRQ3, INT0 to INT7, ADTRG, TMIB, TMCIV, TMRIV, FTCI, FTIA, FTIB, FTIC, FTID, TRGV Values Min Typ 2.5 2.5 2 -- -- -- Max -- -- -- tcyc tsubcyc Figure 13-3 Unit V Test Condition Reference Figure Input pin low width tIL 2 -- -- tcyc tsubcyc Figure 13-3 334 Table 13-8 Serial Interface (SCI1) Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tscyc tSCKH tSCKL tSCKr tSCKf tSOD tSIS tSIH Applicable Pins SCK1 SCK1 SCK1 SCK1 SCK1 SO1 SI1 SI1 Values Min Typ 4 0.4 0.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 60 80 60 80 200 350 -- -- -- -- ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V ns VCC = 4.0 V to 5.5 V Unit tcyc tscyc tscyc ns VCC = 4.0 V to 5.5 V Test Condition Reference Figure Figure 13-4 200 -- 400 -- 200 -- 400 -- Table 13-9 Serial Interface (SCI3) Timing VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Values Item Input clock cycle Asynchronous Synchronous tSCKW tTXD tRXS tRXH Symbol tscyc Min 4 6 0.4 -- -- 200 400 200 400 Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 13-6 ns VCC = 4.0 V to 5.5 V Figure 13-6 tscyc tcyc VCC = 4.0 V to 5.5 V Figure 13-5 Figure 13-6 Unit tcyc Test Conditions Reference Figure Figure 13-5 Input clock pulse width Transmit data delay time (synchronous) Receive data setup time (synchronous) Receive data hold time (synchronous) 335 13.2.6 A/D Converter Characteristics Table 13-10 shows the A/D converter characteristics of the HD6473657, the HD6433657, the HD6433656, the HD6433655, the HD6433654, the HD6433653, and the HD6433652. Table 13-10 A/D Converter Characteristics VCC = AVCC = 2.2 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = -20C to +75C, unless otherwise specified. Item Symbol Applicable Pins AVCC AN0 to AN7 AVCC AVCC Values Min 2.2 Typ -- Max 5.5 Unit V Test Condition Reference Figure 1 Analog power AVCC supply voltage Analog input voltage Analog power supply current AVIN AIOPE AISTOP1 AVSS - 0.3 -- -- -- -- 150 AVCC + 0.3 V 1.5 -- mA A AVCC = 5 V 2 Reference value 3 AISTOP2 Analog input capacitance Allowable signal source impedance Resolution (data length) Nonlinearity error Quantization error Absolute accuracy Conversion time CAIN RAIN AVCC AN0 to AN7 -- -- -- -- -- -- 5 30 5 A pF k -- -- -- -- 12.4 24.8 -- -- -- -- -- -- 8 2.0 0.5 2.5 124 124 bit LSB LSB LSB s AVCC = 2.7 to 5.5 V Notes: 1. Always set AVCC = VCC for the analog power supply voltage. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 336 13.3 Operation Timing Figures 13-1 to 13-9 show timing diagrams. t OSC VIH OSC1 VIL t CPH t CPr t CPL t CPf Figure 13-1 System Clock Input Timing RES VIL tREL Figure 13-2 RES Low Width Timing IRQ0 to IRQ3 INT0 to INT7 ADTRG TMIB, FTIA FTIB TMCIV, FTIC FTID TMRIV FTCI, TRGV VIH VIL t IL t IH Figure 13-3 Input Timing 337 t scyc SCK 1 V IH or V OH* V IL or V OL * t SCKL t SCKf t SOD t SCKH t SCKr SO 1 VOH* VOL * t SIS t SIH SI 1 Notes: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Load conditions are shown in figure 13-7. Figure 13-4 SCI1, SCI2 Input/Output Timing 338 t SCKW SCK 3 t scyc Figure 13-5 SCK3 Input Clock Timing t scyc SCK 3 VIH or VOH * VIL or VOL * t TXD TXD (transmit data) VOH VOL * * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high Output low VOH = 2.0 V VOL = 0.8 V Load conditions are shown in figure 13-7. Figure 13-6 Serial Interface 3 Synchronous Mode Input Output Timing 339 13.4 Output Load Circuit VCC 2.4 k Output pin 30 pF 12 k Figure 13-7 Output Load Condition 340 Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol * 0 -- Modified according to the instruction result Not fixed (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result 341 Table A-1 lists the H8/300L CPU instruction set. Table A-1 Instruction Set Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd Operation @Rn Condition Code IHNZVC ---- ---- B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP Rn 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs 342 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd Operation @Rn Condition Code I HNZVC B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 Rn 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- -- -- -- 2 2 2 2 2 -- (1) (2) (2) ------------ 2 ------------ 2 ---- --* -- -- -- --2 * (3) 2 2 2 2 2 -- (1) (2) (2) ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 2 2 2 2 -- (1) 343 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic MULXU.B Rs, Rd DIVXU.B Rs, Rd Operation @Rn Condition Code IHNZVC B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 2 2 2 Rn 2 2 -- -- -- -- -- -- 14 -- -- (5) (6) -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd ---- 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ---- 0--2 0--2 0--2 0--2 0--2 0--2 0--2 2 SHAR.B Rd B 2 ---- 02 SHLL.B Rd B C 2 ---- 02 SHLR.B Rd B 0 2 ---- 0 0 2 ROTXL.B Rd B C b7 b0 2 ---- 02 ROTXR.B Rd B b7 b0 C 2 ---- 02 344 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic ROTL.B Rd Operation C b7 b0 @Rn Condition Code I HNZVC ---- Rn B 2 02 ROTR.B Rd B C b7 b0 2 ---- 02 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 345 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd Operation @Rn Condition Code IHNZVC B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C Rn 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 ------ ---- 2 ------ ---- 6 ------ ---- 6 ------ ---- 2 ------ ---- 6 ------ ---- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 346 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 Operation Branching Condition @Rn Condition Code I HNZVC B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 2 2 4 2 4 Rn 4 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 4 4 4 2 2 ------------ 6 ------------ 8 ------------ 6 347 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa Mnemonic JSR @Rn Operation @Rn Condition Code IHNZVC -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 -- if R4L0 Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; 2 2 2 2 2 2 Rn 2 ------------ 6 JSR @aa:16 4 ------------ 8 JSR @@aa:8 2 ------------ 8 RTS RTE 2 ------------ 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV 2 ------------ 2 2 2 2 2 2 ------------ 2 2 ------------ 2 4 ------------ 4 Notes: (1) (2) (3) (4) (5) (6) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. The number of states required for execution is 4n + 9 (n = value of R4L). Set to 1 if the divisor is negative; otherwise cleared to 0. Set to 1 if the divisor is zero; otherwise cleared to 0. 348 A.2 Operation Code Map Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 349 Table A-2 Operation Code Map 8 ADD SUB DEC SUBS CMP INC ADDS MOV 9 A B C D E ADDX SUBX F Low High 0 1 2 3 4 5 6 7 0 NOP SLEEP STC LDC ORC XORC ANDC LDC DAA DAS SHLL SHLR ROTXL ROTXR NOT 1 OR XOR AND SHAL SHAR ROTL ROTR NEG 2 MOV 3 BVS JMP BPL BMI 4 BRA BRN BHI BLS BCC BCS BNE BEQ BVC BGE BLT BGT JSR MOV * BLE 5 MULXU DIVXU RTS BSR RTE BST 6 MOV BSET BNOT BCLR BTST BOR BXOR BAND BIST BLD 7 EEPMOV Bit-manipulation instructions BIOR BIXOR BIAND BILD ADD ADDX CMP SUBX OR XOR AND MOV 350 8 9 A B C D E F Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. BSET #0, @FF00 From table A-4: I = L = 2, J = K = M = N= 0 From table A-3: SI = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and onchip RAM is used for stack area. JSR @@ 30 From table A-4: I = 2, J = K = 1, L = M = N = 0 From table A-3: SI = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 351 Table A-3 Number of Cycles in Each Instruction Execution Status (instruction cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 2 or 3* -- Access Location On-Chip Memory 2 On-Chip Peripheral Module -- Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details. 352 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 2 1 1 Word Data Internal Access Operation M N Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 2 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 BCLR #xx:3, @aa:8 2 BCLR Rn, Rd 1 353 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 1 1 2 2 Word Data Internal Access Operation M N Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 1 1 BIXOR #xx:3, @aa:8 2 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd 1 2 2 1 2 1 1 2 2 BNOT #xx:3, @aa:8 2 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd 1 2 2 1 2 2 1 2 2 2 1 1 2 2 BSET #xx:3, @aa:8 2 BSET Rn, Rd BSET Rn, @Rd 1 2 2 354 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 1 1 2 2 1 2 Word Data Internal Access Operation M N Instruction Mnemonic BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 2 CMP CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 12 2n+2* 1 2 2 2 1 Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. 355 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 1 1 1 1 1 1 2 2 Instruction Mnemonic MOV MOV.B @(d:16, Rs), Rd 2 MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd 1 1 2 1 MOV.B Rs, @(d:16, Rd) 2 MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 1 1 2 2 1 1 1 1 1 1 1 1 1 1 12 2 2 MOV.W @(d:16, Rs), Rd 2 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd 1 2 1 MOV.W Rs, @(d:16, Rd) 2 MOV.W Rs, @-Rd MOV.W Rs, @aa:16 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC ROTL ROTR ROTXL ROTXR RTE RTS ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 2 356 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 Word Data Internal Access Operation M N Instruction Mnemonic SHLL SHAL SHAR SHLR SLEEP STC SUB SHLL.B Rd SHAL.B Rd SHAR.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP PUSH SUBX POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR 357 Appendix B Internal I/O Registers B.1 Addresses Register Address Name Bit 7 H'F740 H'F741 H'F742 H'F743 H'F744 H'F770 H'F771 H'F772 H'F773 H'F774 H'F775 H'F776 H'F777 H'F778 H'F779 F'F77A F'F77B H'F77C H'F77D H'F77E H'F77F H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA7 H'FFA8 H'FFA9 H'FFAA H'FFAB SMR BRR SCR3 TDR COM BRR7 TIE TDR7 CHR BRR6 RIE TDR6 PE BRR5 TE TDR5 PM BRR4 RE TDR4 STOP BRR3 MPIE TDR3 MP BRR2 TEIE TDR2 CKS1 BRR1 CKE1 TDR1 CKS0 BRR0 CKE0 TDR0 SCI3 TIER TCSRX FRCH FRCL ICIAE ICFA FRCH7 FRCL7 ICIBE ICFB FRCH6 FRCL6 ICICE ICFC FRCH5 FRCL5 ICIDE ICFD FRCH4 FRCL4 OCIAE OCFA FRCH3 FRCL3 OCIBE OCFB FRCH2 FRCL2 OVIE OVF FRCH1 FRCL1 -- CCLRA FRCH0 FRCL0 Timer X Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name OCRAH/ OCRAH7/ OCRAH6/ OCRAH5/ OCRAH4/ OCRAH3/ OCRAH2/ OCRAH1/ OCRAH0/ OCRBH OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0 OCRAL/ OCRBL TCRX TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL SCR1 SCSR1 SDRU SDRL OCRAL7/ OCRAL6/ OCRAL5/ OCRAL4/ OCRAL3/ OCRAL2/ OCRAL1/ OCRAL0/ OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0 IEDGA -- ICRAH7 ICRAL7 ICRBH7 ICRBL7 ICRCH7 ICRCL7 ICRDH7 ICRDL7 SNC1 -- SDRU7 SDRL7 IEDGB -- ICRAH6 ICRAL6 ICRBH6 ICRBL6 ICRCH6 ICRCL6 ICRDH6 ICRDL6 SNC0 SOL SDRU6 SDRL6 IEDGC -- ICRAH5 ICRAL5 ICRBH5 ICRBL5 ICRCH5 ICRCL5 ICRDH5 ICRDL5 MRKON ORER SDRU5 SDRL5 IEDGD OCRS ICRAH4 ICRAL4 ICRBH4 ICRBL4 ICRCH4 ICRCL4 ICRDH4 ICRDL4 LTCH -- SDRU4 SDRL4 BUFEA OEA ICRAH3 ICRAL3 ICRBH3 ICRBL3 ICRCH3 ICRCL3 ICRDH3 ICRDL3 CKS3 -- SDRU3 SDRL3 BUFEB OEB ICRAH2 ICRAL2 ICRBH2 ICRBL2 ICRCH2 ICRCL2 ICRDH2 ICRDL2 CKS2 -- SDRU2 SDRL2 CKS1 OLVLA ICRAH1 ICRAL1 ICRBH1 ICRBL1 ICRCH1 ICRCL1 ICRDH1 ICRDL1 CKS1 MTRF SDRU1 SDRL1 CKS0 OLVLB ICRAH0 ICRAL0 ICRBH0 ICRBL0 ICRCH0 ICRCL0 ICRDH0 ICRDL0 CKS0 STF SDRU0 SDRL0 SCI1 Notation SCI1: Serial communication interface 1 358 Register Address Name Bit 7 H'FFAC H'FFAD H'FFAE H'FFAF H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD H'FFBE H'FFBF H'FFC0 H'FFC1 H'FFC2 H'FFC3 H'FFC4 H'FFC5 H'FFC6 H'FFC7 H'FFC8 H'FFC9 H'FFCA H'FFCB AMR ADRR ADSR CKS ADR7 ADSF TCRV0 TCSRV TCORA TCORB TCNTV TCRV1 TCSRW TCW CMIEB CMFB TMA TCA TMB1 TCB1/ TLB1 TMA7 TCA7 TMB17 TCB17/ TLB17 SSR RDR TDRE RDR7 Bit Names Bit 6 RDRF RDR6 Bit 5 OER RDR5 Bit 4 FER RDR4 Bit 3 PER RDR3 Bit 2 TEND RDR2 Bit 1 MPBR RDR1 Bit 0 MPBT RDR0 Module Name SCI3 TMA6 TCA6 -- TCB16/ TLB16 TMA5 TCA5 -- TCB15/ TLB15 -- TCA4 -- TCB14/ TLB14 TMA3 TCA3 -- TCB13/ TLB13 TMA2 TCA2 TMB12 TCB12/ TLB12 TMA1 TCA1 TMB11 TCB11/ TLB11 TMA0 TCA0 TMB10 TCB10/ TLB10 Timer A Timer B1 CMIEA CMFA OVIE OVF CCLR1 -- CCLR0 OS3 CKS2 OS2 CKS1 OS1 CKS0 OS0 Timer V TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 -- B6WI TCW7 -- TCWE TCW6 -- B4WI TCW5 TVEG1 TVEG0 TRGE WDON TCW2 -- BOWI TCW1 ICKS0 WRST TCW0 Watchdog timer TCSRWE B2WI TCW4 TCW3 TRGE ADR6 -- -- ADR5 -- -- ADR4 -- CH3 ADR3 -- CH2 ADR2 -- CH1 ADR1 -- CH0 ADR0 -- A/D converter 359 Register Address Name Bit 7 H'FFCC H'FFCD H'FFCE H'FFCF H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC PCR5 PCR6 PCR7 PCR8 PCR9 PCR57 PCR67 PCR77 PCR87 -- PCR1 PCR2 PCR3 PCR17 PCR27 -- PDR5 PDR6 PDR7 PDR8 PDR9 PDRB P57 P67 P77 P87 -- PB7 PDR1 PDR2 PDR3 P17 P27 -- PWCR PWDRU PWDRL -- -- Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name -- -- -- 14-bit PWM PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 -- -- -- -- PWCR0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 P16 P26 -- P15 P25 P35 P55 P65 P75 P85 -- PB5 P14 P24 P34 P54 P64 P74 P84 P94 PB4 P13 P23 P33 P53 P63 P73 P83 P93 PB3 P12 P22 P32 P52 P62 P72 P82 P92 PB2 P11 P21 P31 P51 P61 P71 P81 P91 PB1 P10 P20 P30 P50 P60 P70 P80 P90 PB0 I/O ports P56 P66 P76 P86 -- PB6 I/O ports PCR16 PCR26 -- PCR15 PCR25 PCR35 PCR55 PCR65 PCR75 PCR85 -- PCR14 PCR24 PCR34 PCR54 PCR64 PCR74 PCR84 PCR94 PCR13 PCR23 PCR33 PCR53 PCR63 PCR73 PCR83 PCR93 PCR12 PCR22 PCR32 PCR52 PCR62 PCR72 PCR82 PCR92 PCR11 PCR21 PCR31 PCR51 PCR61 PCR71 PCR81 PCR91 PCR10 PCR20 PCR30 PCR50 PCR60 PCR70 PCR80 PCR90 PCR56 PCR66 PCR76 PCR86 -- 360 Register Address Name Bit 7 H'FFED H'FFEE H'FFEF H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB H'FFFC H'FFFD H'FFFE H'FFFF PMR7 -- PMR1 PMR3 IRQ3 -- PUCR1 PUCR3 PUCR5 PUCR17 -- PUCR57 Bit Names Bit 6 PUCR16 -- PUCR56 STS2 -- -- INTEG6 IENTA IENAD INTEN6 IRRTA IRRAD INTF6 Bit 5 PUCR15 PUCR35 PUCR55 STS1 -- -- INTEG5 -- -- INTEN5 -- -- INTF5 Bit 4 PUCR14 PUCR34 PUCR54 STS0 NESEL -- INTEG4 -- IENSI INTEN4 -- IRRS1 INTF4 Bit 3 PUCR13 PUCR33 PUCR53 LSON DTON IEG3 INTEG3 IEN3 -- INTEN3 IRRI3 -- INTF3 Bit 2 PUCR12 PUCR32 PUCR52 -- MSON IEG2 INTEG2 IEN2 -- INTEN2 IRRI2 -- INTF2 Bit 1 PUCR11 PUCR31 PUCR51 MA1 SA1 IEG1 INTEG1 IEN1 -- INTEN1 IRRI1 -- INTF1 Bit 0 PUCR10 PUCR30 PUCR50 MA0 SA0 IEG0 INTEG0 IEN0 -- INTEN0 IRRI0 -- INTF0 Module Name I/O ports SYSCR1 SSBY SYSCR2 -- IEGR1 IEGR2 IENR1 IENR2 IENR3 IRR1 IRR2 IRR3 -- INTEG7 IENTB1 IENDT INTEN7 IRRTB1 IRRDT INTF7 System control IRQ2 -- IRQ1 -- PWM -- -- -- -- SO1 -- SI1 TMOW SCK1 I/O ports -- -- -- -- TXD -- POF1 I/O ports 361 B.2 Functions Register acronym Register name Address to which the register is mapped Name of on-chip supporting module Timer C TMC--Timer mode register C H'B4 Bit numbers Bit 7 TMC7 Initial value Read/Write 0 R/W 6 TMC6 0 R/W 5 TMC5 0 R/W 4 -- 1 -- 3 -- 1 -- 2 TMC2 0 R/W 1 TMC1 0 R/W 0 TMC0 0 R/W Initial bit values Names of the bits. Dashes (--) indicate reserved bits. Possible types of access R W Read only Write only R/W Read and write Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/64 1 0 0 Internal clock: o/16 1 Internal clock: o/4 1 0 Internal clock: o W /4 1 External event (TMIC): Rising or falling edge Counter up/down control 0 0 TCC is an up-counter 1 TCC is a down-counter 1 * TCC up/down control is determined by input at pin UD. TCC is a down-counter if the UD input is high, and an up-counter if the UD input is low. Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Note: * Don't care Full name of bit Descriptions of bit settings 362 TIER--Timer interrupt enable register Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 H'F770 2 OCIBE 0 R/W 1 OVIE 0 R/W Timer X 0 -- 1 -- OCIAE 0 R/W Timer overflow interrupt enable 0 Interrupt request (FOVI) by OVF is disabled 1 Interrupt request (FOVI) by OVF is enabled Output compare interrupt B enable 0 Interrupt request (OCIB) by OCFB is disabled 1 Interrupt request (OCIB) by OCFB is enabled Output compare interrupt A enable 0 Interrupt request (OCIA) by OCFA is disabled 1 Interrupt request (OCIA) by OCFA is enabled Input capture interrupt D enable 0 Interrupt request (ICID) by ICFD is disabled 1 Interrupt request (ICID) by ICFD is enabled Input capture interrupt C enable 0 Interrupt request (ICIC) by ICFC is disabled 1 Interrupt request (ICIC) by ICFC is enabled Input capture interrupt B enable 0 Interrupt request (ICIB) by ICFB is disabled 1 Interrupt request (ICIB) by ICFB is enabled Input capture interrupt A enable 0 Interrupt request (ICIA) by ICFA is disabled 1 Interrupt request (ICIA) by ICFA is enabled 363 TCSRX--Timer control/status register X Bit Initial value Read/Write 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 H'F771 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* Timer X 0 CCLRA 0 R/W OCFA 0 R/(W)* Counter clear A 0 FRC is not cleared by compare match A 1 FRC is cleared by compare match A Timer overflow 0 [Clearing condition] After reading OVF = 1, cleared by writing 0 to OVF 1 [Setting condition] Set when the FRC value goes from H'FFFF to H'0000 Output compare flag B 0 [Clearing condition] After reading OCFB = 1, cleared by writing 0 to OCFB 1 [Setting condition] Set when FRC matches OCRB Output compare flag A 0 [Clearing condition] After reading OCFA = 1, cleared by writing 0 to OCFA 1 [Setting condition] Set when FRC matches OCRA Input capture flag D 0 [Clearing condition] After reading ICFD = 1, cleared by writing 0 to ICFD 1 [Setting condition] Set by input capture signal Input capture flag C 0 [Clearing condition] After reading ICFC = 1, cleared by writing 0 to ICFC 1 [Setting condition] Set by input capture signal Input capture flag B 0 [Clearing condition] After reading ICFB = 1, cleared by writing 0 to ICFB 1 [Setting condition] When the value of FRC is transferred to ICRB by the input capture signal Input capture flag A 0 [Clearing condition] After reading ICFA = 1, cleared by writing 0 to ICFA 1 [Setting condition] When the value of FRC is transferred to ICRA by the input capture signal Note: * Only 0 can be written, to clear the flag. 364 FRCH--Free-running counter H Bit Initial value Read/Write 7 FRCH7 0 R/W 6 FRCH6 0 R/W 5 FRCH5 0 R/W 4 FRCH4 0 R/W 3 H'F772 2 FRCH2 0 R/W 1 FRCH1 0 R/W Timer X 0 FRCH0 0 R/W FRCH3 0 R/W Count value FRCL--Free-running counter L Bit Initial value Read/Write 7 FRCL7 0 R/W 6 FRCL6 0 R/W 5 FRCL5 0 R/W 4 FRCL4 0 R/W 3 H'F773 2 FRCL2 0 R/W 1 FRCL1 0 R/W Timer X 0 FRCL0 0 R/W FRCL3 0 R/W Count value OCRAH--Output compare register AH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 H'F774 2 1 R/W 1 1 R/W Timer X 0 1 R/W OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0 R/W OCRBH--Output compare register BH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 H'F774 2 1 R/W 1 1 R/W Timer X 0 1 R/W OCRBH7 OCRBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0 R/W 365 OCRAL--Output compare register AL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 H'F775 2 1 R/W 1 1 R/W Timer X 0 1 R/W OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0 R/W OCRBL--Output compare register BL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 H'F775 2 1 R/W 1 1 R/W Timer X 0 1 R/W OCRBL7 OCRBL6 OCRBL5 OCRBL4 OCRBL3 OCRBL2 OCRBL1 OCRBL0 R/W 366 TCRX--Timer control register X Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W H'F776 2 BUFEB 0 R/W 1 CKS1 0 R/W Timer X 0 CKS0 0 R/W Clock select 0 0 Internal clock: o/2 1 Internal clock: o/8 1 0 Internal clock: o/32 1 External clock: rising edge Buffer enable B 0 ICRD is not used as a buffer register for ICRB 1 ICRD is used as a buffer register for OCRB Buffer enable A 0 ICRC is not used as a buffer register for ICRA 1 ICRC is used as a buffer register for OCRA Input edge select D 0 Falling edge of input D is captured 1 Rising edge of input D is captured Input edge select C 0 Falling edge of input C is captured 1 Rising edge of input C is captured Input edge select B 0 Falling edge of input B is captured 1 Rising edge of input B is captured Input edge select A 0 Falling edge of input A is captured 1 Rising edge of input A is captured 367 TOCR--Timer Output compare control register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 H'F777 2 OEB 0 R/W 1 OLVLA 0 R/W Timer X 0 OLVLB 0 R/W OEA 0 R/W Output level B 0 Low level 1 High level Output level A 0 Low level 1 High level Output enable B 0 Output compare B output is disabled 1 Output compare B output is enabled Output enable A 0 Output compare A output is disabled 1 Output compare A output is enabled Output compare register select 0 OCRA is selected 1 OCRB is selected 368 ICRAH--Input capture register AH Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F778 2 0 R 1 0 R Timer X 0 0 R ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0 ICRAL--Input capture register AL Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F779 2 0 R 1 0 R Timer X 0 0 R ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0 ICRBH--Input capture register BH Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77A 2 0 R 1 0 R Timer X 0 0 R ICRBH7 ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0 ICRBL--Input capture register BL Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77B 2 0 R 1 0 R Timer X 0 0 R ICRBL7 ICRBL6 ICRBL5 ICRBL4 ICRBL3 ICRBL2 ICRBL1 ICRBL0 369 ICRCH--Input capture register CH Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77C 2 0 R 1 0 R Timer X 0 0 R ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0 ICRCL--Input capture register CL Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77D 2 0 R 1 0 R Timer X 0 0 R ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0 ICRDH--Input capture register DH Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77E 2 0 R 1 0 R Timer X 0 0 R ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0 ICRDL--Input capture register DL Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R H'F77F 2 0 R 1 0 R Timer X 0 0 R ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0 370 SCR1--Serial control register 1 Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 MRKON 0 R/W 4 LTCH 0 R/W 3 CKS3 0 R/W H'FFA0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Clock select (CKS2 to CKS0) Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Serial Clock Cycle Synchronous Prescaler Division o = 5 MHz o = 2.5 MHz o/1024 204.8 s 409.6 s o/256 51.2 s 102.4 s o/64 12.8 s 25.6 s 6.4 s 12.8 s o/32 3.2 s 6.4 s o/16 1.6 s 3.2 s o/8 0.8 s 1.6 s o/4 -- 0.8 s o/2 Clock source select 0 Clock source is prescaler S, and pin SCK 1 is output pin 1 Clock source is external clock, and pin SCK 1 is input pin* Note: * Input an external clock equivalent to a frequency lower than o/4. LATCH TAIL select 0 HOLD TAIL is output 1 LATCH TAIL is output TAIL MARK control 0 TAIL MARK is not output (synchronous mode) 1 TAIL MARK is output (SSB mode) Operation mode select 1, 0 0 0 8-bit mode 1 16-bit mode 1 0 Continuous clock output mode 1 Reserved 371 SCSR1--Serial control/status register Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- H'FFA1 2 -- 1 -- 1 MTRF 0 R 0 SCI1 STF 0 R/W Start flag 0 Read Write 1 Read Write Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation TAIL MARK transmit flag 0 Idle state and 8- or -16-bit data transfer in progress 1 TAIL MARK transmission in progress Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO1 pin output level is low Write SO1 pin output level changes to low 1 Read SO1 pin output level is high Write SO1 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible. 372 SDRU--Serial data register U Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 H'FFA2 2 SDRU2 R/W 1 SDRU1 R/W SCI1 0 SDRU0 R/W SDRU3 R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data SDRL--Serial data register L Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 H'FFA3 2 SDRL2 R/W 1 SDRL1 R/W SCI1 0 SDRL0 R/W SDRL3 R/W Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Stores transmit and receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data 373 SMR--Serial mode register Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 H'FFA8 2 MP 0 R/W 1 CKS1 0 R/W SCI3 0 CKS0 0 R/W STOP 0 R/W Clock select 0 0 o clock 0 1 o/4 clock 1 0 o/16 clock 1 1 o/64 clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode 374 BRR--Bit rate register Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 H'FFA9 2 BRR2 1 R/W 1 BRR1 1 R/W SCI3 0 BRR0 1 R/W BRR3 1 R/W 375 SCR3--Serial control register 3 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 H'FFAA 2 TEIE 0 R/W 1 CKE1 0 R/W SCI3 0 CKE0 0 R/W MPIE 0 R/W Clock enable Bit 0 Bit 1 CKE1 CKE0 0 0 0 1 1 1 0 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source SCK 3 Pin Function I/O port Internal clock Serial clock output Internal clock Clock output Internal clock Reserved (Do not specify this combination) Clock input External clock Serial clock input External clock Reserved (Do not specify this combination) Reserved (Do not specify this combination) Transmit end interrupt enable 0 1 Transmit end interrupt request (TEI) disabled Transmit end interrupt request (TEI) enabled Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (normal receive operation) [Clearing conditions] When data is received in which the multiprocessor bit is set to 1 Multiprocessor interrupt request enabled The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with the multiprocessor bit set to 1 is received. 1 Receive enable 0 1 Receive operation disabled (RXD pin is I/O port) Receive operation enabled (RXD pin is receive data pin) Transmit enable 0 1 Transmit operation disabled (TXD pin is transmit data pin) Transmit operation enabled (TXD pin is transmit data pin) Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable Transmit data empty interrupt request (TXI) disabled 0 1 Transmit data empty interrupt request (TXI) enabled 376 TDR--Transmit data register Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 H'FFAB 2 TDR2 1 R/W 1 TDR1 1 R/W SCI3 0 TDR0 1 R/W TDR3 1 R/W Data for transfer to TSR 377 SSR--Serial status register Bit Initial value Read/Write 7 TDRE 1 R/(W) * H'FFAC 6 RDRF 0 R/(W) * SCI3 1 MPBR 0 R 0 MPBT 0 R/W 5 OER 0 R/(W) * 4 FER 0 R/(W) * 3 PER 0 R/(W) * 2 TEND 1 R Multiprocessor bit transfer 0 1 A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor bit receive 0 1 0 Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmission in progress [Clearing conditions] * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmission ended [Setting conditions] * When bit TE in serial control register 3 (SCR3) is cleared to 0 * When bit TDRE is set to 1 when the last bit of a transmit character is sent Transmit end 1 Parity error 0 1 Reception in progress or completed normally [Clearing conditions] After reading PER = 1, cleared by writing 0 to PER A parity error has occurred during reception [Setting conditions] When the number of 1 bits in the receive data plus parity bit does not match the parity designated by the parity mode bit (PM) in the serial mode register (SMR) Reception in progress or completed normally [Clearing conditions] After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception [Setting conditions] When the stop bit at the end of the receive data is checked for a value of 1 at completion of reception, and the stop bit is 0 Reception in progress or completed [Clearing conditions] After reading OER = 1, cleared by writing 0 to OER An overrun error has occurred during reception [Setting conditions] When the next serial reception is completed with RDRF set to 1 Framing error 0 1 Overrun error 0 1 Receive data register full 0 There is no receive data in RDR [Clearing conditions] * After reading RDRF = 1, cleared by writing 0 to RDRF * When RDR data is read by an instruction There is receive data in RDR [Setting conditions] When reception ends normally and receive data is transferred from RSR to RDR 1 Transmit data register empty 0 Transmit data written in TDR has not been transferred to TSR [Clearing conditions] * After reading TDRE = 1, cleared by writing 0 to TDRE * When data is written to TDR by an instruction Transmit data has not been written to TDR, or transmit data written in TDR has been transferred to TSR [Setting conditions] * When bit TE in serial control register 3 (SCR3) is cleared to 0 * When data is transferred from TDR to TSR 1 Note: * Only a write of 0 for flag clearing is possible. 378 RDR--Receive data register Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 H'FFAD 2 RDR2 0 R 1 RDR1 0 R SCI3 0 RDR0 0 R RDR3 0 R TMA--Timer mode register A Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 H'FFB0 2 TMA2 0 R/W 1 TMA1 0 R/W Timer A 0 TMA0 0 R/W TMA3 0 R/W Clock output select 0 0 0 o/32 1 o/16 1 0 o/8 1 o/4 1 0 0 o W /32 1 o W /16 1 0 o W /8 1 o W /4 Internal clock select Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 0 o/8192 0 PSS 1 o/4096 PSS o/2048 PSS 1 0 o/512 PSS 1 1 0 0 o/256 PSS 1 o/128 PSS o/32 1 0 PSS o/8 1 PSS 0 0 0 1s 1 PSW 1 0.5 s PSW 0.25 s 1 0 PSW 0.03125 s 1 PSW 1 0 0 PSW and TCA are reset 1 1 0 1 Function Interval timer Time base 379 TCA--Timer counter A Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R H'FFB1 2 TCA2 0 R 1 TCA1 0 R Timer A 0 TCA0 0 R Count value TMB1--Timer mode register B1 Bit Initial value Read/Write 7 TMB17 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFB2 2 TMB12 0 R/W 1 TMB11 0 R/W Timer B1 0 TMB10 0 R/W Auto-reload function select 0 Interval timer function selected 1 Auto-reload function selected Clock select 0 0 0 Internal clock: o/8192 1 Internal clock: o/2048 1 0 Internal clock: o/512 1 Internal clock: o/256 1 0 0 Internal clock: o/64 1 Internal clock: o/16 1 0 Internal clock: o/4 1 External event (TMIB): Rising or falling edge 380 TCB1--Timer counter B1 Bit Initial value Read/Write 7 TCB17 0 R 6 TCB16 0 R 5 TCB15 0 R 4 TCB14 0 R 3 H'FFB3 2 TCB12 0 R 1 TCB11 0 R Timer B1 0 TCB10 0 R TCB13 0 R Count value TLB1--Timer load register B1 Bit Initial value Read/Write 7 TLB17 0 W 6 TLB16 0 W 5 TLB15 0 W 4 TLB14 0 W 3 H'FFB3 2 TLB12 0 W 1 TLB11 0 W Timer B1 0 TLB10 0 W TLB13 0 W Reload value 381 TCRV0--Timer control register V0 Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 H'FFB8 2 CKS2 0 R/W 1 CKS1 0 R/W Timer V 0 CKS0 0 R/W CCLR0 0 R/W Clock select TCRV0 TCRV1 Bit 2 Bit 1 Bit 0 Bit 0 Description CKS2 CKS1 CKS0 ICKS0 -- Clock input disabled 0 0 0 0 Internal clock: o/4, falling edge 1 1 Internal clock: o/8, falling edge 1 0 0 Internal clock: o/16, falling edge 1 Internal clock: o/32, falling edge 1 0 Internal clock: o/64, falling edge 1 Internal clock: o/128, falling edge 0 1 0 -- Clock input disabled 1 -- External clock: rising edge 1 0 -- External clock: falling edge 1 -- External clock: rising and falling edges Counter clear 1 and 0 0 Clearing is disabled Cleared by compare match A 1 Cleared by compare match B Cleared by rising edge of external reset input Timer overflow interrupt enable 0 Interrupt request (OVI) from OVF disabled 1 Interrupt request (OVI) from OVF enabled Compare match interrupt enable A 0 Interrupt request (CMIA) from CMFA disabled 1 Interrupt request (CMIA) from CMFA enabled Compare match interrupt enable B 0 Interrupt request (CMIB) from CMFB disabled 1 Interrupt request (CMIB) from CMFB enabled 382 TCSRV--Timer control/status register V Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W H'FFB9 2 OS2 0 R/W 1 OS1 0 R/W Timer V 0 OS0 0 R/W Output select 0 0 No change at compare match A 1 0 output at compare match A 1 0 1 output at compare match A 1 Output toggles at compare match A Output select 0 0 No change at compare match B 1 0 output at compare match B 1 0 1 output at compare match B 1 Output toggles at compare match B Timer overflow flag 0 [Clearing condition] After reading OVF = 1, cleared by writing 0 to OVF 1 [Setting condition] Set when TCNTV overflows from H'FF to H'00 Compare match flag A 0 [Clearing condition] After reading CMFA = 1, cleared by writing 0 to CMFA 1 [Setting condition] Set when the TCNTV value matches the TCORA value Compare match flag B 0 [Clearing condition] After reading CMFB = 1, cleared by writing 0 to CMFB 1 [Setting condition] Set when the TCNTV value matches the TCORB value Note: * Only a write of 0 for flag clearing is possible. 383 TCORA--Time constant register A Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFBA 2 1 R/W 1 1 R/W Timer V 0 1 R/W TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB--Time constant register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFBB 2 1 R/W 1 1 R/W Timer V 0 1 R/W TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV--Timer counter V Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFBC 2 0 R/W 1 0 R/W Timer V 0 0 R/W TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 384 TCRV1--Timer control register V1 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 TVEG1 0 R/W 3 H'FFBD 2 TRGE 0 R/W 1 -- 1 -- Timer V 0 ICKS0 0 R/W TVEG0 0 R/W Internal clock select Selects the TCNTV clock source, with bits CKS2 to CKS0 in TCRV0 TRGV input enable 0 TCNTV counting is not triggered by input at the TRGV pin, and does not stop when TCNTV is cleared by compare match 1 TCNTV counting is triggered by input at the TRGV pin, and stops when TCNTV is cleared by compare match TRGV input edge select 0 0 TRGV trigger input is disabled 1 Rising edge is selected 1 0 Falling edge is selected 1 Rising and falling edges are both selected 385 TCSRW--Timer control/status register W Bit Initial value Read/Write 7 B6WI 1 R 6 TCWE 0 R/(W)* 5 B4WI 1 R 4 TCSRWE 0 R/(W)* 3 B2WI 1 R H'FFBE 2 WDON 0 R/(W) * Watchdog timer 1 B0WI 1 R 0 WRST 0 R/(W) * Watchdog timer reset 0 [Clearing conditions] * Reset by RES pin * When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 [Setting condition] When TCW overflows and a reset signal is generated Bit 0 write inhibit 0 Bit 0 is write-enabled 1 Bit 0 is write-protected Watchdog timer on 0 Watchdog timer operation is disabled 1 Watchdog timer operation is enabled Bit 2 write inhibit 0 Bit 2 is write-enabled 1 Bit 2 is write-protected Timer control/status register W write enable 0 Data cannot be written to TCSRW bits 2 and 0 1 Data can be written to TCSRW bits 2 and 0 Bit 4 write inhibit 0 Bit 4 is write-enabled 1 Bit 4 is write-protected Timer counter W write enable 0 Data cannot be written to TCW bit 8 1 Data can be written to TCW bit 8 Bit 6 write inhibit 0 Bit 6 is write-enabled 1 Bit 6 is write-protected Note: * Write is permitted only under certain conditions. 386 TCW--Timer counter W Bit Initial value Read/Write 7 TCW7 0 R/W 6 TCW6 0 R/W 5 TCW5 0 R/W 4 TCW4 0 R/W 3 H'FFBF 2 TCW2 0 R/W Watchdog timer 1 TCW1 0 R/W 0 TCW0 0 R/W TCW3 0 R/W Count value 387 AMR--A/D mode register Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 CH3 0 R/W H'FFC4 2 CH2 0 R/W 1 A/D converter 0 CH0 0 R/W CH1 0 R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 0 1 1 0 0 1 1 0 0 1 1 External trigger select Bit 0 CH0 * 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Reserved Reserved Reserved Reserved * Don't care 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 CKS Conversion Period 0 62/o 1 31/o Conversion Time o = 2 MHz o = 5 MHz 31 s 15.5 s 12.4 s -- *1 Note: * Operation is not guaranteed with a conversion time of less than 12.4 s. Select a setting that gives a conversion time of 12.4 s or more. 388 ADRR--A/D result register Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R 3 ADR3 R H'FFC5 2 ADR2 R A/D converter 1 ADR1 R 0 ADR0 R Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed A/D conversion result ADSR--A/D start register Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFC6 2 -- 1 -- A/D converter 1 -- 1 -- 0 -- 1 -- A/D status flag 0 Read Indicates completion of A/D conversion Write Stops A/D conversion 1 Read Indicates A/D conversion in progress Write Starts A/D conversion 389 PWCR--PWM control register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFD0 2 -- 1 -- 1 -- 1 -- 14-bit PWM 0 PWCR0 0 W Clock select 0 The input clock is o/2 (to* = 2/o). The conversion period is 16,384/o, with a minimum modulation width of 1/o. 1 The input clock is o/4 (to* = 4/o). The conversion period is 32,768/o, with a minimum modulation width of 2/o. Note: * to: Period of PWM input clock PWDRU--PWM data register U Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W H'FFD1 2 0 W 1 0 W 14-bit PWM 0 0 W PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0 Upper 6 bits of data for generating PWM waveform PWDRL--PWM data register L Bit Initial value Read/Write 7 PWDRL7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'FFD2 2 0 W 1 0 W 14-bit PWM 0 0 W PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 Lower 8 bits of data for generating PWM waveform 390 PDR1--Port data register 1 Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W H'FFD4 2 P12 0 R/W 1 P11 0 R/W I/O ports 0 P10 0 R/W PDR2--Port data register 2 Bit Initial value Read/Write 7 P2 7 0 R/W 6 P2 6 0 R/W 5 P2 5 0 R/W 4 P2 4 0 R/W 3 P2 3 0 R/W H'FFD5 2 P22 0 R/W 1 P21 0 R/W I/O ports 0 P20 0 R/W PDR3--Port data register 3 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 P3 5 0 R/W 4 P3 4 0 R/W 3 P3 3 0 R/W H'FFD6 2 P32 0 R/W 1 P31 0 R/W I/O ports 0 P30 0 R/W PDR5--Port data register 5 Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W H'FFD8 2 P52 0 R/W 1 P51 0 R/W I/O ports 0 P50 0 R/W PDR6--Port data register 6 Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W H'FFD9 2 P62 0 R/W 1 P61 0 R/W I/O ports 0 P60 0 R/W 391 PDR7--Port data register 7 Bit Initial value Read/Write 7 P7 7 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W H'FFDA 2 P72 0 R/W 1 P71 0 R/W I/O ports 0 P70 0 R/W PDR8--Port data register 8 Bit Initial value Read/Write 7 P8 7 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W H'FFDB 2 P82 0 R/W 1 P81 0 R/W I/O ports 0 P80 0 R/W PDR9--Port data register 9 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 P94 0 R/W 3 P93 0 R/W H'FFDC 2 P92 0 R/W 1 P91 0 R/W I/O ports 0 P90 0 R/W PDRB--Port data register B Bit Initial value Read/Write R R R R R 7 PB 7 6 PB 6 5 PB 5 4 PB 4 3 PB 3 H'FFDD 2 PB 2 R 1 PB 1 R I/O ports 0 PB 0 R PCR1--Port control register 1 Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W H'FFE4 2 PCR12 0 W 1 PCR11 0 W I/O ports 0 PCR10 0 W Port 1 input/output select 0 Input pin 1 Output pin 392 PCR2--Port control register 2 Bit Initial value Read/Write 7 PCR2 7 0 W 6 PCR2 6 0 W 5 PCR2 5 0 W 4 PCR2 4 0 W 3 PCR2 3 0 W H'FFE5 2 PCR22 0 W 1 PCR21 0 W I/O ports 0 PCR20 0 W Port 2 input/output select 0 Input pin 1 Output pin PCR3--Port control register 3 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 PCR3 5 0 W 4 PCR34 0 W 3 0 W H'FFE6 2 0 W 1 PCR31 0 W I/O ports 0 PCR30 0 W PCR3 3 PCR32 PCR5--Port control register 5 Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 H'FFE8 2 PCR52 0 W 1 PCR51 0 W I/O ports 0 PCR50 0 W PCR53 0 W Port 5 input/output select 0 Input pin 1 Output pin 393 PCR6--Port control register 6 Bit Initial value Read/Write 7 PCR6 7 0 W 6 PCR6 6 0 W 5 PCR6 5 0 W 4 PCR6 4 0 W 3 H'FFE9 2 PCR6 2 0 W 1 PCR6 1 0 W I/O ports 0 PCR6 0 0 W PCR6 3 0 W Port 6 input/output select 0 Input pin 1 Output pin PCR7--Port control register 7 Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W H'FFEA 2 PCR72 0 W 1 PCR71 0 W I/O ports 0 PCR70 0 W Port 7 input/output select 0 Input pin 1 Output pin PCR8--Port control register 8 Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 H'FFEB 2 PCR82 0 W 1 PCR81 0 W I/O ports 0 PCR80 0 W PCR83 0 W Port 8 input/output select 0 Input pin 1 Output pin 394 PCR9--Port control register 9 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 PCR9 4 0 W 3 0 W H'FFEC 2 0 W 1 PCR91 0 W I/O ports 0 PCR90 0 W PCR9 3 PCR92 Port 9 input/output select 0 Input pin 1 Output pin PUCR1--Port pull-up control register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFED 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR3--Port pull-up control register 3 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 0 R/W 4 0 R/W 3 0 R/W H'FFEE 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR35 PUCR34 PUCR3 3 PUCR32 PUCR31 PUCR30 PUCR5--Port pull-up control register 5 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFEF 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 395 SYSCR1--System control register 1 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 H'FFF0 2 -- 1 -- System control 1 MA1 1 R/W 0 MA0 1 R/W LSON 0 R/W Active (medium-speed) mode clock select 0 0 oosc /16 0 1 oosc /32 1 0 oosc /64 1 1 o osc /128 Low speed on flag 0 The CPU operates on the system clock (o) 1 The CPU operates on the subclock (oSUB ) Standby timer select 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 * * Wait time = 131,072 states Software standby 0 * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode Note: * Don't care 396 SYSCR2--System control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 DTON 0 R/W H'FFF1 2 MSON 0 R/W System control 1 SA1 0 R/W 0 SA0 0 R/W Subactive mode clock select 0 0 o W /8 1 o W /4 1 * o W /2 Medium speed on flag 0 * Operates in active (high-speed) mode after exit from standby, watch, or sleep mode * Operates in sleep (high-speed) mode if a SLEEP instruction is executed in active mode 1 * Operates in active (medium-speed) mode after exit from standby, watch, or sleep mode * Operates in sleep (medium-speed) mode if a SLEEP instruction is executed in active mode Direct transfer on flag 0 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 * When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1 * When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1 Noise elimination sampling frequency select 0 Sampling rate is oOSC /16 1 Sampling rate is oOSC /4 Note: * Don't care 397 IEGR1--Interrupt edge select register 1 Bit Initial value Read/Write 7 -- 0 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 IEG3 0 R/W H'FFF2 2 IEG2 0 R/W System control 1 IEG1 0 R/W 0 IEG0 0 R/W IRQ0 edge select 0 Falling edge of IRQ0 pin input is detected 1 Rising edge of IRQ0 pin input is detected IRQ1 edge select 0 Falling edge of IRQ1 pin input is detected 1 Rising edge of IRQ1 pin input is detected IRQ2 edge select 0 Falling edge of IRQ2 pin input is detected 1 Rising edge of IRQ2 pin input is detected IRQ3 edge select 0 Falling edge of IRQ3 pin input is detected 1 Rising edge of IRQ3 pin input is detected 398 IEGR2--Interrupt edge select register 2 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFF3 2 0 R/W 1 0 System control 0 0 R/W INTEG7 INTEG6 INTEG5 INTEG4 INTEG3 INTEG2 INTEG1 INTEG0 R/W INT4 to INT0 edge select 0 Falling edge of INTn pin input is detected 1 Rising edge of INTn pin input is detected (n = 4 to 0) INT5 edge select 0 Falling edge of INT5 and ADTRG pin input is detected 1 Rising edge of INT5 and ADTRG pin input is detected (n = 5 to 0) INT6 edge select 0 Falling edge of INT6 and TMIB pin input is detected 1 Rising edge of INT6 and TMIB pin input is detected INT7 edge select 0 Falling edge of INT7 and TMIY pin input is detected 1 Rising edge of INT7 and TMIY pin input is detected 399 IENR1--Interrupt enable register 1 Bit Initial value Read/Write 7 IENTB1 0 R/W 6 IENTA 0 R/W 5 -- 0 -- 4 -- 1 -- 3 IEN3 0 R/W H'FFF4 2 IEN2 0 R/W System control 1 IEN1 0 R/W 0 IEN0 0 R/W IRQ3 to IRQ0 interrupt enable 0 Disables IRQ3 to IRQ0 interrupt requests 1 Enables IRQ3 to IRQ0 interrupt requests Timer A interrupt enable 0 Disables timer A interrupt requests 1 Enables timer A interrupt requests Timer B1 interrupt enable 0 Disables timer B1 interrupt requests 1 Enables timer B1 interrupt requests 400 IENR2--Interrupt enable register 2 Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 -- 4 IENS1 0 R/W 3 -- 0 -- H'FFF5 2 -- 0 -- System control 1 -- 0 -- 0 -- 0 -- SCI1 interrupt enable 0 Disables SCI1 interrupt requests 1 Enables SCI1 interrupt requests A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transfer interrupt enable 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt requests IENR3--Interrupt enable register 3 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFF6 2 0 R/W System control 1 0 R/W 0 0 R/W INTEN7 INTEN6 INTEN5 INTEN4 INTEN3 INTEN2 INTEN1 INTEN0 INT7 to INT0 interrupt enable 0 Disables INT7 to INT0 interrupt requests 1 Enables INT7 to INT0 interrupt requests 401 IRR1--Interrupt request register 1 Bit Initial value Read/Write 7 IRRTB1 0 R/W * 6 IRRTA 0 R/W * 5 -- 0 -- 4 -- 1 -- 3 IRRI3 0 H'FFF7 2 IRRI2 0 R/W * System control 1 IRRI1 0 R/W * 0 IRRI0 0 R/W * R/W * IRQ3 to IRQ0 interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 1 [Setting condition] When pin IRQn is set for interrupt input and the designated signal edge is input (n = 3 to 0) Timer A interrupt request flag 0 [Clearing condition] When IRRTA = 1, it is cleared by writing 0 1 [Setting condition] When timer counter A overflows from H'FF to H'00 Timer B1 interrupt request flag 0 [Clearing condition] When IRRTB1 = 1, it is cleared by writing 0 1 [Setting condition] When timer counter B1 overflows from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. 402 IRR2--Interrupt request register 2 Bit Initial value Read/Write 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 -- 0 -- 4 IRRS1 0 R/W * 3 -- 0 -- H'FFF8 2 -- 0 -- System control 1 -- 0 -- 0 -- 0 -- SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed A/D converter interrupt request flag 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 1 [Setting condition] When A/D conversion is completed and ADSF is cleared to 0 in ADSR Direct transfer interrupt request flag 0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct transfer is made Note: * Only a write of 0 for flag clearing is possible. 403 IRR3--Interrupt request register 3 t tial value ead/Write 7 INTF7 0 R/W * 6 INTF6 0 R/W * 5 INTF5 0 R/W * 4 INTF4 0 R/W 3 INTF3 0 R/W * H'FFF9 2 INTF2 0 R/W * 1 INTF1 0 R/W * System control 0 INTF0 0 R/W * INT7 to INT0 interrupt request flag 0 [Clearing condition] When INTFn = 1, it is cleared by writing 0 1 [Setting condition] When the designated signal edge is input at pin INTn (n = 7 to 0) ote: * Only a write of 0 for flag clearing is possible. 404 PMR1--Port mode register 1 Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 PWM 0 R/W 3 -- 0 -- H'FFFC 2 -- 1 -- 1 -- 0 -- I/O ports 0 TMOW 0 R/W P10/TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P14/PWM pin function switch 0 Functions as P14 I/O pin 1 Functions as PWM output pin P15/IRQ1 pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ1 input pin P16/IRQ2 pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ2 input pin P17/IRQ3/TRGV pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ3/TRGV input pin 405 PMR3--Port mode register 3 Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- H'FFFD 2 SO1 0 R/W 1 SI1 0 R/W I/O ports 0 SCK1 0 R/W P30/SCK1 pin function switch 0 Functions as P30 I/O pin 1 Functions as SCK1 I/O pin P31/SI1 pin function switch 0 Functions as P31 I/O pin 1 Functions as SI1 input pin P32/SO1 pin function switch 0 Functions as P32 I/O pin 1 Functions as SO1 output pin PMR7--Port mode register 7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFFF 2 TXD 0 R/W 1 -- 0 -- I/O ports 0 POF1 0 R/W P32/SO1 pin PMOS control 0 CMOS output 1 NMOS open-drain output P22/TXD pin function switch (TXD) 0 Functions as P22 I/O pin 1 Functions as TXD output pin 406 Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 SBY RES (low level during reset and in standby mode) VCC VCC PUCR17 PMR17 P1n PDR17 Internal data bus VSS PCR17 IRQ3 Timer V module PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 TRGV Figure C-1 (a) Port 1 Block Diagram (Pin P17) 407 SBY RES (low level during reset and in standby mode) VCC VCC PUCR16 PMR16 P1n PDR16 Internal data bus VSS PCR16 IRQ2 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (b) Port 1 Block Diagram (Pin P16) 408 SBY (low level during reset and in standby mode) VCC VCC RES PUCR15 PMR15 P15 PDR15 Internal data bus VSS PCR15 IRQ1 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (c) Port 1 Block Diagram (Pin P15) 409 RES SBY (low level during reset and in standby mode) PUCR14 VCC VCC PMR14 PWM module PWM P14 PDR14 Internal data bus VSS PCR14 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (d) Port 1 Block Diagram (Pin P14) 410 SBY (low level during reset and in standby mode) VCC VCC RES PUCR1n P1n PDR1n Internal data bus VSS PCR1n PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 n= 3 to 1 Figure C-1 (e) Port 1 Block Diagram (Pins P13 to P11) 411 RES SBY (low level during reset and in standby mode) PUCR10 VCC VCC PMR10 Timer A module TMOW P10 PDR10 Internal data bus VSS PCR10 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C-1 (f) Port 1 Block Diagram (Pin P10) 412 C.2 Block Diagrams of Port 2 SBY (low level during reset and in standby mode) VCC P2n PDR2n Internal data bus VSS PCR2n PDR2: PCR2: n= 7 to 3 Port data register 2 Port control register 2 Figure C-2 (a) Port 2 Block Diagram (Pins P27 to P23) 413 SBY PMR72 VCC SCI3 module TXD Internal data bus P22 PDR22 VSS PCR22 PDR2: PCR2: PMR7: Port data register 2 Port control register 2 Port mode register 7 Figure C-2 (b) Port 2 Block Diagram (Pin P22) 414 SBY VCC SCI3 module RE RXD P21 PDR21 Internal data bus VSS PCR21 PDR2: PCR2: Port data register 2 Port control register 2 Figure C-2 (c) Port 2 Block Diagram (Pin P21) 415 SBY SCI3 module VCC SCKIE SCKOE SCKO SCKI P20 PDR20 Internal data bus VSS PCR20 PDR2: PCR2: Port data register 2 Port control register 2 Figure C-2 (d) Port 2 Block Diagram (Pin P20) 416 C.3 Block Diagrams of Port 3 SBY (low level during reset and in standby mode) VCC VCC RES PUCR3n P3n PDR3n Internal data bus VSS PCR3n PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 n= 5 to 3 Figure C-3 (a) Port 3 Block Diagram (Pins P35 to P33) 417 RES SBY (low level during reset and in standby mode) SCI1 module SO1 PMR70 PUCR32 VCC VCC PMR32 P32 PDR32 Internal data bus VSS PCR32 PDR3: PCR3: PMR3: PMR7: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port mode register 7 Port pull-up control register 3 Figure C-3 (b) Port 3 Block Diagram (Pin P32) 418 SBY (low level during reset and in standby mode) VCC VCC RES PUCR31 PMR31 P31 PDR31 Internal data bus VSS PCR31 SCI1 module SI1 PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (c) Port 3 Block Diagram (Pin P31) 419 RES SBY (low level during reset and in standby mode) SCI1 module CKS3 SCK0 SCK1 PUCR30 VCC VCC PMR30 Internal data bus P30 PDR30 VSS PCR30 PDR3: PCR3: PMR3: PUCR3: Port data register 3 Port control register 3 Port mode register 3 Port pull-up control register 3 Figure C-3 (d) Port 3 Block Diagram (Pin P30) 420 C.4 Block Diagrams of Port 5 SBY (low level during reset and in standby mode) VCC VCC RES PUCR5n P5n PDR5n VSS PCR5n Internal data bus INT module INTn PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 n = 7, 4 to 0 Figure C-4 (a) Port 5 Block Diagram (Pins P57 and P54 to P50) 421 SBY (low level during reset and in standby mode) VCC VCC PUCR56 Timer B1 module TMIB Internal data bus P56 PDR56 VSS PCR56 INT module INT6 PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Figure C-4 (b) Port 5 Block Diagram (Pin P56) 422 SBY (low level during reset and in standby mode) VCC VCC RES A/D module ADTRG Internal data bus PUCR55 P55 PDR55 VSS PCR55 INT module INT5 PDR5: Port data register 5 PCR5: Port control register 5 PUCR5: Port pull-up control register 5 Figure C-4 (c) Port 5 Block Diagram (Pin P55) 423 C.5 Block Diagram of Port 6 SBY (low level during reset and in standby mode) VCC P6n PDR6n Internal data bus VSS PCR6n PDR6: PCR6: Port data register 6 Port control register 6 n = 7 to 0 Figure C-5 Port 6 Block Diagram (Pins P67 to P60) 424 C.6 Block Diagrams of Port 7 SBY (low level during reset and in standby mode) VCC P7n PDR7n Internal data bus VSS PCR7n PDR7: Port data register 7 PCR7: Port control register 7 n = 7 or 3 to 0 Figure C-6 (a) Port 7 Block Diagram (Pins P77 and P73 to P70) 425 SBY (low level during reset and in standby mode) Timer V module VCC TMOV PDR76 0S3 to 0S0 P76 VSS PCR76 Internal data bus PDR7: Port data register 7 PCR7: Port control register 7 Figure C-6 (b) Port 7 Block Diagram (Pin P76) 426 SBY (low level during reset and in standby mode) VCC P75 PDR75 Internal data bus VSS PCR75 Timer V module TMCIV PDR7: Port data register 7 PCR7: Port control register 7 Figure C-6 (c) Port 7 Block Diagram (Pin P75) 427 SBY (low level during reset and in standby mode) VCC P74 PDR74 Internal data bus VSS PCR74 Timer V module TMRIV PDR7: Port data register 7 PCR7: Port control register 7 Figure C-6 (d) Port 7 Block Diagram (Pin P74) 428 C.7 Block Diagrams of Port 8 SBY (low level during reset and in standby mode) VCC P87 PDR87 Internal data bus VSS PCR87 PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (a) Port 8 Block Diagram (Pin P87) 429 SBY (low level during reset and in standby mode) VCC P86 PDR86 Internal data bus VSS PCR86 Timer X module FTID PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (b) Port 8 Block Diagram (Pin P86) 430 SBY (low level during reset and in standby mode) VCC P85 PDR85 Internal data bus VSS PCR85 Timer X module FTIC PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (c) Port 8 Block Diagram (Pin P85) 431 SBY (low level during reset and in standby mode) VCC P84 PDR84 Internal data bus VSS PCR84 Timer X module FTIB PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (d) Port 8 Block Diagram (Pin P84) 432 SBY (low level during reset and in standby mode) VCC P83 PDR83 Internal data bus VSS PCR83 Timer X module FTIA PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (e) Port 8 Block Diagram (Pin P83) 433 SBY (low level during reset and in standby mode) VCC Timer X module OEB FTOB P82 PDR82 VSS PCR82 Internal data bus PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (f) Port 8 Block Diagram (Pin P82) 434 SBY (low level during reset and in standby mode) VCC Timer X module OEA FTOA P81 PDR81 VSS PCR81 Internal data bus PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (g) Port 8 Block Diagram (Pin P81) 435 SBY (low level during reset and in standby mode) VCC P80 PDR80 Internal data bus VSS PCR80 Timer X module FTCI PDR8: Port data register 8 PCR8: Port control register 8 Figure C-7 (h) Port 8 Block Diagram (Pin P80) 436 C.8 Block Diagram of Port 9 SBY (low level during reset and in standby mode) VCC P4n PDR9n Internal data bus VSS PCR9n PDR9: Port data register 9 PCR9: Port control register 9 n = 4 to 0 Figure C-8 Port 9 Block Diagram (Pins P94 to P90) 437 C.9 Block Diagram of Port B Internal data bus PBn A/D module DEC AMR3 to AMR0 VIN n = 7 to 0 Figure C-9 Port B Block Diagram (Pins PB7 to PB0) 438 Appendix D Port States in the Different Processing States Table D-1 Port States Overview Port P17 to P10 Reset Sleep Subsleep Standby Retained Retained Retained Retained Retained Retained Retained Retained Watch Subactive Active Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions Functions High Retained impedance High Retained impedance* High Retained impedance High Retained impedance* High Retained impedance* High Retained impedance High Retained impedance High Retained impedance High Retained impedance Retained P27 to P20 High impedance Retained P35 to P30 High impedance Retained P57 to P50 High impedance Retained P67 to P60 High impedance Retained P77 to P70 High impedance Retained P87 to P80 High impedance Retained P94 to P90 High impedance High High High High High High PB7 to PB0 High impedance impedance impedance impedance impedance impedance impedance Note: * High level output when MOS pull-up is in on state. 439 Appendix E Product Code Lineup Table E-1 Product Lineup Product Type H8/3657 ZTAT Standard products Product Code Mark Code HD6473657W HD6473657X HD6473657H HD6473657F Mask ROM version HD6433657W HD6433657X HD6433657H HD6433657F H8/3656 Mask ROM version HD6433656W HD6433656X HD6433656H HD6433656F H8/3655 Mask ROM version HD6433655W HD6433655X HD6433655H HD6433655F H8/3654 Mask ROM version HD6433654W HD6433654X HD6433654H HD6433654F H8/3653 Mask ROM version HD6433653W HD6433653X HD6433653H HD6433653F H8/3652 Mask ROM version HD6433652W HD6433652X HD6433652H HD6433652F Note: (***) indicates the ROM code. HD6473657W HD6473657X HD6473657H HD6473657F HD6433657(***)W HD6433657(***)X HD6433657(***)H HD6433657(***)F HD6433656(***)W HD6433656(***)X HD6433656(***)H HD6433656(***)F HD6433655(***)W HD6433655(***)X HD6433655(***)H HD6433655(***)F HD6433654(***)W HD6433654(***)X HD6433654(***)H HD6433654(***)F HD6433653(***)W HD6433653(***)X HD6433653(***)H HD6433653(***)F HD6433652(***)W HD6433652(***)X HD6433652(***)H HD6433652(***)F Package (Hitachi Package Code) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 80-pin TQFP (TFP-80C) 80-pin TQFP (TFP-80F) 80-pin QFP (FP-80A) 80-pin QFP (FP-80B) 440 Appendix F Package Dimensions Dimensional drawings of H8/3657 Series packages TFP-80C, TFP-80F, FP-80A, and FP-80B are shown in figures F-1 to F-4 below. Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Hitachi Semiconductor Packages Manual take precedence and are considered correct. 14.0 0.2 12 60 61 14.0 0.2 41 40 Unit: mm 80 1 0.22 0.05 0.20 0.04 20 21 0.5 1.20 Max 0.10 M 1.25 1.00 0.17 0.05 0.15 0.04 1.0 0 - 8 0.5 0.1 0.10 Dimension including the plating thickness Base material dimension Figure F-1 TFP-80C Package Dimensions 0.10 0.10 441 16.0 0.2 14 Unit: mm 41 40 0.65 60 61 16.0 0.2 80 1 0.32 0.08 0.30 0.06 21 20 0.13 M 0.83 0.17 0.05 0.15 0.04 1.20 Max 1.00 1.0 0.10 Dimension including the plating thickness Base material dimension Figure F-2 TFP-80F Package Dimensions 0.10 0.10 0.5 0.1 0 to 8 442 17.2 0.3 14 Unit: mm 41 40 0.65 60 61 17.2 0.3 80 1 0.32 0.08 0.30 0.06 21 20 0.12 M 0.83 2.70 3.05 Max 0.17 0.05 0.15 0.04 1.6 0.10 +0.15 -0.10 0 - 8 0.8 0.3 0.10 Dimension including the plating thickness Base material dimension Figure F-3 FP-80A Package Dimensions 443 24.8 0.4 20 64 65 18.8 0.4 41 40 14 80 1 0.37 0.08 0.35 0.06 24 0.15 M 25 3.10 Max 0.8 0.17 0.05 0.15 0.04 0.8 2.70 2.4 1.0 0 - 10 0.20 +0.10 -0.20 0.15 Dimension including the plating thickness Base material dimension 1.2 0.2 Figure F-4 FP-80B Package Dimensions 444 H8/3657 Series Hardware Manual Publication Date: Published by: 1st Edition, October 1997 Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. |
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